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-rw-r--r--testsuite/synth/issue1096/my_entity.vhdl26
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diff --git a/testsuite/synth/issue1096/my_entity.vhdl b/testsuite/synth/issue1096/my_entity.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+package mask_pkg is
+ constant MASK: std_logic_vector(0 downto 0);
+end package;
+
+package body mask_pkg is
+ constant MASK: std_logic_vector(0 downto 0) := "0";
+end package body;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity my_entity is
+ port (
+ data: out std_logic_vector(0 downto 0)
+ );
+end entity;
+
+use work.mask_pkg.all;
+
+architecture arch of my_entity is
+begin
+ data <= MASK;
+end architecture;