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-rw-r--r--testsuite/synth/issue1050/top.vhdl36
1 files changed, 36 insertions, 0 deletions
diff --git a/testsuite/synth/issue1050/top.vhdl b/testsuite/synth/issue1050/top.vhdl
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+++ b/testsuite/synth/issue1050/top.vhdl
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+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity child is
+ port (
+ O1: out std_logic;
+ O2: out std_logic
+ );
+end entity child;
+
+architecture rtl of child is
+begin
+ O1 <= '0';
+ O2 <= '1';
+end architecture rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity top is
+ port (
+ O: out std_logic
+ );
+end entity top;
+
+architecture rtl of top is
+ component child is
+ port (
+ O1: out std_logic;
+ O2: out std_logic
+ );
+ end component child;
+begin
+ inst : child port map(O1 => O);
+end architecture rtl;