9 files changed, 381 insertions, 1 deletions
diff --git a/testsuite/synth/fsm01/fsm_3s.vhdl b/testsuite/synth/fsm01/fsm_3s.vhdl
new file mode 100644
index 000000000..bd27a0ffd
--- /dev/null
+++ b/testsuite/synth/fsm01/fsm_3s.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fsm_3s is
+  port (clk : std_logic;
+        rst : std_logic;
+        d : std_logic;
+        done : out std_logic);
+end fsm_3s;
+
+architecture behav of fsm_3s is
+  type state_t is (S0_1, S1_0, S2_1);
+  signal s : state_t;
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        s <= S0_1;
+        done <= '0';
+      else
+        --  Reset by default
+        s <= S0_1;
+        done <= '0';
+        case s is
+          when S0_1 =>
+            if d = '1' then
+              s <= S1_0;
+            end if;
+          when S1_0 =>
+            if d = '0' then
+              s <= S2_1;
+            end if;
+          when S2_1 =>
+            if d = '1' then
+              done <= '1';
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/fsm_5s.vhdl b/testsuite/synth/fsm01/fsm_5s.vhdl
new file mode 100644
index 000000000..8e7b387c7
--- /dev/null
+++ b/testsuite/synth/fsm01/fsm_5s.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fsm_5s is
+  port (clk : std_logic;
+        rst : std_logic;
+        d : std_logic;
+        done : out std_logic);
+end fsm_5s;
+
+architecture behav of fsm_5s is
+  type state_t is (S0_1, S1_0, S2_0, S3_1, S4_0);
+  signal s : state_t;
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        s <= S0_1;
+        done <= '0';
+      else
+        --  Reset by default
+        s <= S0_1;
+        done <= '0';
+        case s is
+          when S0_1 =>
+            if d = '1' then
+              s <= S1_0;
+            end if;
+          when S1_0 =>
+            if d = '0' then
+              s <= S2_0;
+            end if;
+          when S2_0 =>
+            if d = '0' then
+              s <= S3_1;
+            end if;
+          when S3_1 =>
+            if d = '1' then
+              s <= S4_0;
+            end if;
+          when S4_0 =>
+            if d = '0' then
+              done <= '1';
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/fsm_6s.vhdl b/testsuite/synth/fsm01/fsm_6s.vhdl
new file mode 100644
index 000000000..1daf0a39f
--- /dev/null
+++ b/testsuite/synth/fsm01/fsm_6s.vhdl
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fsm_6s is
+  port (clk : std_logic;
+        rst : std_logic;
+        d : std_logic;
+        done : out std_logic);
+end fsm_6s;
+
+architecture behav of fsm_6s is
+  type state_t is (S0_1, S1_0, S2_0, S3_1, S4_0, S5_1);
+  signal s : state_t;
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        s <= S0_1;
+        done <= '0';
+      else
+        --  Reset by default
+        s <= S0_1;
+        done <= '0';
+        case s is
+          when S0_1 =>
+            if d = '1' then
+              s <= S1_0;
+            end if;
+          when S1_0 =>
+            if d = '0' then
+              s <= S2_0;
+            end if;
+          when S2_0 =>
+            if d = '0' then
+              s <= S3_1;
+            end if;
+          when S3_1 =>
+            if d = '1' then
+              s <= S4_0;
+            end if;
+          when S4_0 =>
+            if d = '0' then
+              s <= S5_1;
+            end if;
+          when S5_1 =>
+            if d = '1' then
+              done <= '1';
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/fsm_7s.vhdl b/testsuite/synth/fsm01/fsm_7s.vhdl
new file mode 100644
index 000000000..fb65410d8
--- /dev/null
+++ b/testsuite/synth/fsm01/fsm_7s.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fsm_7s is
+  port (clk : std_logic;
+        rst : std_logic;
+        d : std_logic;
+        done : out std_logic);
+end fsm_7s;
+
+architecture behav of fsm_7s is
+  type state_t is (S0_1, S1_0, S2_0, S3_1, S4_0, S5_1, S6_0);
+  signal s : state_t;
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        s <= S0_1;
+        done <= '0';
+      else
+        --  Reset by default
+        s <= S0_1;
+        done <= '0';
+        case s is
+          when S0_1 =>
+            if d = '1' then
+              s <= S1_0;
+            end if;
+          when S1_0 =>
+            if d = '0' then
+              s <= S2_0;
+            end if;
+          when S2_0 =>
+            if d = '0' then
+              s <= S3_1;
+            end if;
+          when S3_1 =>
+            if d = '1' then
+              s <= S4_0;
+            end if;
+          when S4_0 =>
+            if d = '0' then
+              s <= S5_1;
+            end if;
+          when S5_1 =>
+            if d = '1' then
+              s <= S6_0;
+            end if;
+          when S6_0 =>
+            if d = '0' then
+              done <= '1';
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/tb_fsm_3s.vhdl b/testsuite/synth/fsm01/tb_fsm_3s.vhdl
new file mode 100644
index 000000000..919d77910
--- /dev/null
+++ b/testsuite/synth/fsm01/tb_fsm_3s.vhdl
@@ -0,0 +1,44 @@
+entity tb_fsm_3s is
+end tb_fsm_3s;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_fsm_3s is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal done : std_logic;
+begin
+  dut: entity work.fsm_3s
+    port map (
+      done => done,
+      d => din,
+      clk => clk,
+      rst => rst);
+
+  process
+    constant dat : std_logic_vector := b"101_101_1100";
+    constant res : std_logic_vector := b"001_001_0000";
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    din <= '0';
+    pulse;
+    assert done = '0' severity failure;
+    --  Test the whole sequence.
+    rst <= '0';
+    for i in dat'range loop
+      din <= dat (i);
+      pulse;
+      assert done = res(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/tb_fsm_5s.vhdl b/testsuite/synth/fsm01/tb_fsm_5s.vhdl
new file mode 100644
index 000000000..853628cbd
--- /dev/null
+++ b/testsuite/synth/fsm01/tb_fsm_5s.vhdl
@@ -0,0 +1,44 @@
+entity tb_fsm_5s is
+end tb_fsm_5s;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_fsm_5s is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal done : std_logic;
+begin
+  dut: entity work.fsm_5s
+    port map (
+      done => done,
+      d => din,
+      clk => clk,
+      rst => rst);
+
+  process
+    constant dat : std_logic_vector := b"10010_10010_11000";
+    constant res : std_logic_vector := b"00001_00001_00000";
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    din <= '0';
+    pulse;
+    assert done = '0' severity failure;
+    --  Test the whole sequence.
+    rst <= '0';
+    for i in dat'range loop
+      din <= dat (i);
+      pulse;
+      assert done = res(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/tb_fsm_6s.vhdl b/testsuite/synth/fsm01/tb_fsm_6s.vhdl
new file mode 100644
index 000000000..86d123041
--- /dev/null
+++ b/testsuite/synth/fsm01/tb_fsm_6s.vhdl
@@ -0,0 +1,44 @@
+entity tb_fsm_6s is
+end tb_fsm_6s;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_fsm_6s is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal done : std_logic;
+begin
+  dut: entity work.fsm_6s
+    port map (
+      done => done,
+      d => din,
+      clk => clk,
+      rst => rst);
+
+  process
+    constant dat : std_logic_vector := b"100101_100101_110001";
+    constant res : std_logic_vector := b"000001_000001_000000";
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    din <= '0';
+    pulse;
+    assert done = '0' severity failure;
+    --  Test the whole sequence.
+    rst <= '0';
+    for i in dat'range loop
+      din <= dat (i);
+      pulse;
+      assert done = res(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/tb_fsm_7s.vhdl b/testsuite/synth/fsm01/tb_fsm_7s.vhdl
new file mode 100644
index 000000000..9981680ea
--- /dev/null
+++ b/testsuite/synth/fsm01/tb_fsm_7s.vhdl
@@ -0,0 +1,44 @@
+entity tb_fsm_7s is
+end tb_fsm_7s;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_fsm_7s is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal done : std_logic;
+begin
+  dut: entity work.fsm_7s
+    port map (
+      done => done,
+      d => din,
+      clk => clk,
+      rst => rst);
+
+  process
+    constant dat : std_logic_vector := b"1001010_1001010_1100010";
+    constant res : std_logic_vector := b"0000001_0000001_0000000";
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    din <= '0';
+    pulse;
+    assert done = '0' severity failure;
+    --  Test the whole sequence.
+    rst <= '0';
+    for i in dat'range loop
+      din <= dat (i);
+      pulse;
+      assert done = res(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/testsuite.sh b/testsuite/synth/fsm01/testsuite.sh
index 08d7ff60f..875ae0a23 100755
--- a/testsuite/synth/fsm01/testsuite.sh
+++ b/testsuite/synth/fsm01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in fsm_2s fsm_4s; do
+for t in fsm_2s fsm_3s fsm_4s fsm_5s fsm_6s fsm_7s; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean