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Diffstat (limited to 'testsuite/synth/comp01/and6.vhdl')
-rw-r--r-- | testsuite/synth/comp01/and6.vhdl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/synth/comp01/and6.vhdl b/testsuite/synth/comp01/and6.vhdl new file mode 100644 index 000000000..2aadd5261 --- /dev/null +++ b/testsuite/synth/comp01/and6.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity and6 is + port (i0, i1, i2, i3, i4, i5 : std_logic; + o : out std_logic); +end and6; + +architecture behav of and6 is + signal t1, t2 : std_logic; +begin + a1: entity work.and3 + port map (i0, i1, i2, t1); + a2: entity work.and3 + port map (i3, i4, i5, t2); + o <= t1 and t2; +end behav; |