diff options
Diffstat (limited to 'testsuite/pyunit')
-rw-r--r-- | testsuite/pyunit/Current.vhdl | 53 | ||||
-rw-r--r-- | testsuite/pyunit/SimpleEntity.vhdl | 7 | ||||
-rw-r--r-- | testsuite/pyunit/dom/Expressions.py | 70 | ||||
-rw-r--r-- | testsuite/pyunit/dom/Literals.py | 49 |
4 files changed, 177 insertions, 2 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl new file mode 100644 index 000000000..5a677546e --- /dev/null +++ b/testsuite/pyunit/Current.vhdl @@ -0,0 +1,53 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity entity_1 is + generic ( + FREQ : real := 100.0; + BITS : positive := 8 + ); + port ( + Clock: in std_logic; + Reset: in std_logic := '0'; + Q: out std_logic_vector(BITS - 1 downto 0) + ); + + constant fire : boolean := True; +begin + wood <= fire; +end entity entity_1; + +architecture behav of entity_1 is + constant MAX : positive := -25; + signal rst : std_logic := 'U'; + + type newInt is range -4 to 3; + subtype uint8 is integer range 0 to 255; + + function foo(a : integer; b : boolean) return bit is + begin + + end function; + + alias bar is boolean; +begin + process(Clock) + begin + if rising_edge(Clock) then + if Reset = '1' then + Q <= (others => '0'); + else + Q <= std_logic_vector(unsigned(Q) + 1); + end if; + end if; + end process; +end architecture behav; + +package package_1 is + constant ghdl : float := (3, 5, 0 => 5, 3 => 4, name => 10); -- 2.3; +end package; + +package body package_1 is + constant ghdl : float := (1); -- => 2, 4 => 5, others => 10); -- .5; +end package body; diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl index 9997c8d6d..931599086 100644 --- a/testsuite/pyunit/SimpleEntity.vhdl +++ b/testsuite/pyunit/SimpleEntity.vhdl @@ -4,7 +4,7 @@ use ieee.numeric_std.all; entity entity_1 is generic ( - FREQ : real := 100.0; + FREQ : real := (100.0 * 1024.0 * 1024.0); BITS : positive := 8 ); port ( @@ -15,11 +15,14 @@ entity entity_1 is end entity entity_1; architecture behav of entity_1 is + signal Reset_n : std_logic; begin + Reset_n <= (not Reset); + process(Clock) begin if rising_edge(Clock) then - if Reset = '1' then + if Reset_n = '0' then Q <= (others => '0'); else Q <= std_logic_vector(unsigned(Q) + 1); diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py new file mode 100644 index 000000000..3a4f658af --- /dev/null +++ b/testsuite/pyunit/dom/Expressions.py @@ -0,0 +1,70 @@ +from pathlib import Path +from textwrap import dedent +from unittest import TestCase + +from pyGHDL.dom.DesignUnit import Package + +from pyGHDL.dom import Expression +from pyGHDL.dom.Misc import Design, Document +from pyGHDL.dom.Symbol import SimpleObjectSymbol +from pyGHDL.dom.Object import Constant +from pyGHDL.dom.Expression import InverseExpression + +if __name__ == "__main__": + print("ERROR: you called a testcase declaration file as an executable module.") + print("Use: 'python -m unitest <testcase module>'") + exit(1) + + +class Expressions(TestCase): + _root = Path(__file__).resolve().parent.parent + + def test_NotExpression(self): + self._filename: Path = self._root / "{className}.vhdl".format(className=self.__class__.__name__) + + sourceCode = dedent("""\ + package package_1 is + constant c0 : boolean := not true; + end package; + """) + + with self._filename.open(mode="w", encoding="utf-8") as file: + file.write(sourceCode) + + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + package: Package = design.Documents[0].Packages[0] + item: Constant = package.DeclaredItems[0] + default: Expression = item.DefaultExpression + self.assertTrue(isinstance(default, InverseExpression)) + self.assertTrue(isinstance(default.Operand, SimpleObjectSymbol)) + self.assertTrue(default.Operand.SymbolName == "true") + + # def test_Aggregare(self): + # self._filename: Path = self._root / "{className}.vhdl".format(className=self.__class__.__name__) + # + # sourceCode = dedent("""\ + # package package_1 is + # constant c0 : integer_vector := (0, 1, 2); 0 =>); + # constant c1 : integer_vector := (0 => 0, 1 => 1, 2 => 2); + # constant c3 : integer_vector := (a => 0, b => 1, c => 2); + # constant c3 : integer_vector := (0 to 2 => 3, 3 to 4 => 2); + # constant c2 : integer_vector := (others => 0); + # end package; + # """) + # + # with self._filename.open(mode="w", encoding="utf-8") as file: + # file.write(sourceCode) + # + # design = Design() + # document = Document(self._filename) + # design.Documents.append(document) + # + # package: Package = design.Documents[0].Packages[0] + # item: Constant = package.DeclaredItems[0] + # default: Expression = item.DefaultExpression + # self.assertTrue(isinstance(default, InverseExpression)) + # self.assertTrue(isinstance(default.Operand, SimpleObjectSymbol)) + # self.assertTrue(default.Operand.SymbolName == "true") diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py new file mode 100644 index 000000000..7eb80abaa --- /dev/null +++ b/testsuite/pyunit/dom/Literals.py @@ -0,0 +1,49 @@ +from pathlib import Path +from textwrap import dedent +from unittest import TestCase + +from pyGHDL.dom.Misc import Design, Document +from pyGHDL.dom.Object import Constant +from pyGHDL.dom.Literal import IntegerLiteral + + +if __name__ == "__main__": + print("ERROR: you called a testcase declaration file as an executable module.") + print("Use: 'python -m unitest <testcase module>'") + exit(1) + + +class Literals(TestCase): + _root = Path(__file__).resolve().parent.parent + + def test_IntegerLiteral(self): + self._filename: Path = self._root / "{className}.vhdl".format(className=self.__class__.__name__) + + sourceCode = dedent("""\ + package package_1 is + constant c0 : integer := 0; + constant c1 : integer := 1; + constant c2 : integer := 1024; + constant c3 : integer := 1048576; + end package; + """) + expected = (0, 1, 1024, 1048576) + + with self._filename.open(mode="w", encoding="utf-8") as file: + file.write(sourceCode) + + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(len(design.Documents[0].Packages), 1) + package = design.Documents[0].Packages[0] + self.assertTrue(package.Name == "package_1") + self.assertEqual(len(package.DeclaredItems), len(expected)) + for i in range(len(expected)): + item: Constant = package.DeclaredItems[i] + self.assertTrue(isinstance(item, Constant)) + self.assertTrue(item.Name == "c{}".format(i)) + self.assertTrue(item.SubType.SymbolName == "integer") + self.assertTrue(isinstance(item.DefaultExpression, IntegerLiteral)) + self.assertTrue(item.DefaultExpression.Value == expected[i]) |