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Diffstat (limited to 'testsuite/pyunit/SimpleEntity.vhdl')
-rw-r--r-- | testsuite/pyunit/SimpleEntity.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl new file mode 100644 index 000000000..a26a6357c --- /dev/null +++ b/testsuite/pyunit/SimpleEntity.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.numeric_std.all; + +entity e1 is + generic ( + BITS : positive := 8 + ); + port ( + Clock: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(BITS - 1 downto 0) + ); +end entity e1; + +architecture behav of e1 is +begin + process(Clock) + begin + if rising_edge(Clock) then + if Reset = '1' then + Q <= (others => '0'); + else + Q <= std_logic_vector(unsigned(Q) + 1); + end if; + end if; + end process; +end architecture behav; |