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-rw-r--r--testsuite/pyunit/Current.vhdl17
1 files changed, 16 insertions, 1 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index c0c66b0e9..1f1e6c51c 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -151,9 +151,24 @@ begin
begin
inst: component Case0Dummy;
- when others =>
+ when 1 | 2 =>
constant G5 : boolean := False;
begin
+ inst: component Case12Dummy;
+
+ when 3 to 4 =>
+ constant G6 : boolean := False;
+ begin
+ inst: component Case34Dummy;
+
+ when 5 to 6 | 8 to 9 =>
+ constant G7 : boolean := False;
+ begin
+ inst: component Case5689Dummy;
+
+ when others =>
+ constant G8 : boolean := False;
+ begin
inst: component OthersDummy;
end generate;
end architecture behav;