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-rw-r--r--testsuite/pyunit/Current.vhdl22
1 files changed, 20 insertions, 2 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index d364a2b2e..f11ab764a 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -128,15 +128,33 @@ begin
genIf: if True generate
constant G0 : boolean := False;
begin
-
+ inst: IfDummy;
elsif False generate
constant G1 : boolean := False;
begin
-
+ inst: ElsifDummy;
else generate
constant G2 : boolean := False;
begin
+ inst: ElseDummy;
+ end generate;
+
+ genFor: for I in 0 to 3 generate
+ constant G3 : boolean := False;
+ begin
+ inst: ForDummy;
+ end generate;
+
+ genCase: case selector generate
+ when 0 =>
+ constant G4 : boolean := False;
+ begin
+ inst: Case0Dummy;
+ when others =>
+ constant G5 : boolean := False;
+ begin
+ inst: OthersDummy;
end generate;
end architecture behav;