3 files changed, 62 insertions, 0 deletions
diff --git a/testsuite/gna/issue1612/exposep.vhdl b/testsuite/gna/issue1612/exposep.vhdl
new file mode 100644
index 000000000..1078d2865
--- /dev/null
+++ b/testsuite/gna/issue1612/exposep.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity expose_problem is
+  port (
+    arg : in std_logic_vector);
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity expose is
+  generic (
+    ARG : std_logic_vector);
+end entity;
+
+architecture rtl of expose is
+
+begin
+  expose_problem_1 : entity work.expose_problem
+    port map (
+      arg => ARG
+      );
+end architecture;
diff --git a/testsuite/gna/issue1612/repro.vhdl b/testsuite/gna/issue1612/repro.vhdl
new file mode 100644
index 000000000..cf884522b
--- /dev/null
+++ b/testsuite/gna/issue1612/repro.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity expose_problem is
+  port (
+    arg : in std_logic_vector);
+end entity;
+
+architecture behav of expose_problem is
+begin
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity expose is
+  generic (
+    ARG : std_logic_vector := x"56");
+end entity;
+
+architecture rtl of expose is
+
+begin
+  expose_problem_1 : entity work.expose_problem
+    port map (
+      arg => ARG
+      );
+end architecture;
diff --git a/testsuite/gna/issue1612/testsuite.sh b/testsuite/gna/issue1612/testsuite.sh
new file mode 100755
index 000000000..2d3f46835
--- /dev/null
+++ b/testsuite/gna/issue1612/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze repro.vhdl
+elab_simulate expose
+
+clean
+
+echo "Test successful"