3 files changed, 60 insertions, 0 deletions
diff --git a/testsuite/gna/issue227/repro.vhdl b/testsuite/gna/issue227/repro.vhdl
new file mode 100644
index 000000000..394fb9251
--- /dev/null
+++ b/testsuite/gna/issue227/repro.vhdl
@@ -0,0 +1,21 @@
+entity test is
+end entity test;
+
+architecture rtl of test is
+
+  type test_t is record
+    t1 : natural;
+    t2 : natural;
+  end record test_t;
+
+  constant C_TEST_T : test_t :=
+    (
+      t1 => 1,
+      t2 => 2);
+
+  constant C_TEST : bit_vector(0 to 7) :=
+    (C_TEST_T.t1 => '1', others => '0');
+
+begin
+
+end architecture rtl;
diff --git a/testsuite/gna/issue227/test.vhdl b/testsuite/gna/issue227/test.vhdl
new file mode 100644
index 000000000..327f902fe
--- /dev/null
+++ b/testsuite/gna/issue227/test.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity test is
+end entity test;
+
+architecture rtl of test is
+
+  type test_t is record
+    t1 : natural;
+    t2 : natural;
+  end record test_t;
+
+  constant C_TEST_T : test_t :=
+    (
+      t1 => 1,
+      t2 => 2);
+
+  constant C_TEST : std_ulogic_vector(0 to 7) :=
+    (C_TEST_T.t1 => '1', others => '0');
+
+begin
+
+end architecture rtl;
diff --git a/testsuite/gna/issue227/testsuite.sh b/testsuite/gna/issue227/testsuite.sh
new file mode 100755
index 000000000..f0ada08a4
--- /dev/null
+++ b/testsuite/gna/issue227/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate test
+
+analyze --ieee=synopsys test.vhdl
+elab_simulate --ieee=synopsys test
+
+clean
+
+echo "Test successful"