aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/gna/ticket94
diff options
context:
space:
mode:
Diffstat (limited to 'testsuite/gna/ticket94')
-rw-r--r--testsuite/gna/ticket94/apkg.vhd10
-rw-r--r--testsuite/gna/ticket94/asrc.vhd14
-rw-r--r--testsuite/gna/ticket94/build.sh10
-rw-r--r--testsuite/gna/ticket94/tb.vhd49
-rw-r--r--testsuite/gna/ticket94/tb1.vhd32
-rw-r--r--testsuite/gna/ticket94/tb2.vhd29
-rw-r--r--testsuite/gna/ticket94/tb3.vhd28
-rw-r--r--testsuite/gna/ticket94/tb4.vhd31
-rwxr-xr-xtestsuite/gna/ticket94/testsuite.sh45
9 files changed, 248 insertions, 0 deletions
diff --git a/testsuite/gna/ticket94/apkg.vhd b/testsuite/gna/ticket94/apkg.vhd
new file mode 100644
index 000000000..09eba9559
--- /dev/null
+++ b/testsuite/gna/ticket94/apkg.vhd
@@ -0,0 +1,10 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package apkg is
+
+ component acomp is
+ port (x: in std_ulogic; y: out std_ulogic);
+ end component;
+
+end apkg;
diff --git a/testsuite/gna/ticket94/asrc.vhd b/testsuite/gna/ticket94/asrc.vhd
new file mode 100644
index 000000000..d65c812ea
--- /dev/null
+++ b/testsuite/gna/ticket94/asrc.vhd
@@ -0,0 +1,14 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity acomp is
+ port (x: in std_ulogic; y: out std_ulogic);
+end entity;
+
+architecture aarch of acomp is
+begin
+
+ y <= x;
+
+end architecture;
diff --git a/testsuite/gna/ticket94/build.sh b/testsuite/gna/ticket94/build.sh
new file mode 100644
index 000000000..a5bf6750e
--- /dev/null
+++ b/testsuite/gna/ticket94/build.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+set -e
+
+cmd() { echo "$*" ; $* ; }
+
+GHDL=${GHDL:-ghdl}
+cmd $GHDL -a --work=alib asrc.vhd
+cmd $GHDL -a tb.vhd
+cmd $GHDL -e tb
diff --git a/testsuite/gna/ticket94/tb.vhd b/testsuite/gna/ticket94/tb.vhd
new file mode 100644
index 000000000..313d59c8d
--- /dev/null
+++ b/testsuite/gna/ticket94/tb.vhd
@@ -0,0 +1,49 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+library alib;
+use alib.acomp;
+
+entity tb is
+
+end;
+
+architecture arch of tb is
+
+ signal clk: std_logic := '0';
+ signal lclk: std_ulogic;
+
+ signal stop: boolean := false;
+ signal lclk_count: integer := 0;
+
+ component acomp is
+ port (x: in std_ulogic; y: out std_ulogic);
+ end component;
+
+begin
+
+ clk <= not clk after 10 ns when (not stop) else '0';
+
+ ainst: acomp
+ port map (clk, lclk);
+
+ process (lclk) is
+ begin
+ if rising_edge(lclk) then
+ lclk_count <= lclk_count + 1;
+ end if;
+ end process;
+
+ process is
+ begin
+ report "start test";
+ wait for 1 ms;
+ report "end test";
+ report "lclk_count = " & integer'image(lclk_count);
+ assert lclk_count > 20000 report "test failed";
+ if lclk_count > 20000 then report "test passed"; end if;
+ stop <= true;
+ wait;
+ end process;
+
+end architecture;
diff --git a/testsuite/gna/ticket94/tb1.vhd b/testsuite/gna/ticket94/tb1.vhd
new file mode 100644
index 000000000..b0b901cfc
--- /dev/null
+++ b/testsuite/gna/ticket94/tb1.vhd
@@ -0,0 +1,32 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+library alib;
+use alib.acomp;
+
+entity tb1 is
+end;
+
+architecture arch of tb1 is
+
+ signal a, b : std_logic := '0';
+ component acomp is
+ port (x: in std_ulogic; y: out std_ulogic);
+ end component;
+
+begin
+ ainst: acomp
+ port map (a, b);
+
+ process is
+ begin
+ a <= '0';
+ wait for 1 ns;
+ assert b = '0' report "component is missing" severity failure;
+ a <= '1';
+ wait for 1 ns;
+ assert b = '1' report "component is missing" severity failure;
+ wait;
+ end process;
+
+end architecture;
diff --git a/testsuite/gna/ticket94/tb2.vhd b/testsuite/gna/ticket94/tb2.vhd
new file mode 100644
index 000000000..0c52aa1b6
--- /dev/null
+++ b/testsuite/gna/ticket94/tb2.vhd
@@ -0,0 +1,29 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+library alib;
+use alib.acomp;
+
+entity tb2 is
+end;
+
+architecture arch of tb2 is
+
+ signal a, b : std_logic := '0';
+
+begin
+ ainst: alib.apkg.acomp
+ port map (a, b);
+
+ process is
+ begin
+ a <= '0';
+ wait for 1 ns;
+ assert b = '0' report "component is missing" severity failure;
+ a <= '1';
+ wait for 1 ns;
+ assert b = '1' report "component is missing" severity failure;
+ wait;
+ end process;
+
+end architecture;
diff --git a/testsuite/gna/ticket94/tb3.vhd b/testsuite/gna/ticket94/tb3.vhd
new file mode 100644
index 000000000..9cef08e29
--- /dev/null
+++ b/testsuite/gna/ticket94/tb3.vhd
@@ -0,0 +1,28 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+library alib;
+
+entity tb3 is
+end;
+
+architecture arch of tb3 is
+
+ signal a, b : std_logic := '0';
+
+begin
+ ainst: alib.apkg.acomp
+ port map (a, b);
+
+ process is
+ begin
+ a <= '0';
+ wait for 1 ns;
+ assert b = '0' report "component is missing" severity failure;
+ a <= '1';
+ wait for 1 ns;
+ assert b = '1' report "component is missing" severity failure;
+ wait;
+ end process;
+
+end architecture;
diff --git a/testsuite/gna/ticket94/tb4.vhd b/testsuite/gna/ticket94/tb4.vhd
new file mode 100644
index 000000000..d981701b5
--- /dev/null
+++ b/testsuite/gna/ticket94/tb4.vhd
@@ -0,0 +1,31 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+library alib;
+
+entity tb4 is
+end;
+
+architecture arch of tb4 is
+
+ signal a, b : std_logic := '0';
+ component acomp is
+ port (x: in std_ulogic; y: out std_ulogic);
+ end component;
+
+begin
+ ainst: acomp
+ port map (a, b);
+
+ process is
+ begin
+ a <= '0';
+ wait for 1 ns;
+ assert b = '0' report "component is missing" severity failure;
+ a <= '1';
+ wait for 1 ns;
+ assert b = '1' report "component is missing" severity failure;
+ wait;
+ end process;
+
+end architecture;
diff --git a/testsuite/gna/ticket94/testsuite.sh b/testsuite/gna/ticket94/testsuite.sh
new file mode 100755
index 000000000..796dd6979
--- /dev/null
+++ b/testsuite/gna/ticket94/testsuite.sh
@@ -0,0 +1,45 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+# Original test
+analyze --work=alib asrc.vhd
+analyze tb.vhd
+elab_simulate tb
+
+# Reproducer - entity would be visible in the absence of the component
+analyze tb1.vhd
+elab_simulate tb1
+
+# Reproducer - entity is directly visible
+analyze --work=alib apkg.vhd
+analyze tb2.vhd
+elab_simulate tb2
+
+# Reproducer - entity is in the same library. (93c)
+analyze tb3.vhd
+elab_simulate tb3
+
+# Reproducer - entity in a different library, not visible.
+analyze tb4.vhd
+elab_simulate_failure tb4
+elab_simulate --syn-binding tb4
+
+clean
+clean alib
+
+# Reproducer - entity is in the same library (93)
+GHDL_STD_FLAGS=--std=93
+
+analyze --work=alib asrc.vhd
+analyze --work=alib apkg.vhd
+analyze tb3.vhd
+elab_simulate_failure tb3
+
+# But still works with --syn-binding
+elab_simulate --syn-binding tb3
+
+clean
+clean alib
+
+echo "Test successful"