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-rw-r--r--testsuite/gna/issue792/dut.vhdl21
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diff --git a/testsuite/gna/issue792/dut.vhdl b/testsuite/gna/issue792/dut.vhdl
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+++ b/testsuite/gna/issue792/dut.vhdl
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+entity dut is
+ port(
+ a : in string(1 to 1)
+ );
+end entity dut;
+architecture a of dut is
+ component dut_internal
+ port(
+ a : in string;
+ b : in string
+ );
+ end component dut_internal;
+ signal b : string(1 to 1);
+begin
+ inst : dut_internal
+ port map (
+ a => a
+ -- b => b
+ );
+end architecture a;
+