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-rw-r--r--testsuite/gna/issue641/repro4.vhdl20
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/gna/issue641/repro4.vhdl b/testsuite/gna/issue641/repro4.vhdl
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+++ b/testsuite/gna/issue641/repro4.vhdl
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+entity repro4b is
+ port (b : bit_vector);
+end entity;
+
+architecture a of repro4b is
+ signal c : b'subtype;
+begin
+ c <= (others => '0');
+end architecture;
+
+entity repro4 is
+end entity;
+
+architecture tb of repro4 is
+ signal s : bit_vector(7 downto 0);
+begin
+ DUT: entity work.repro4b
+ port map (b => s);
+end architecture;
+