3 files changed, 92 insertions, 0 deletions
diff --git a/testsuite/gna/issue520/alias.vhdl b/testsuite/gna/issue520/alias.vhdl
new file mode 100644
index 000000000..9b1d98c56
--- /dev/null
+++ b/testsuite/gna/issue520/alias.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity alias_extname_driving_signal is
+  port(
+    clk : in std_logic
+  );
+end alias_extname_driving_signal;
+
+architecture primary of alias_extname_driving_signal is
+  signal counter : unsigned(15 downto 0) := (others => '0');
+begin
+ counter <= (counter + 1) when rising_edge(clk);
+end architecture primary;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity alias_tb is
+end alias_tb;
+
+architecture primary of alias_tb is
+  signal clk : std_logic := '0';
+  signal vector16 : unsigned(15 downto 0);
+begin
+  clk <= not clk after 10 ns;
+
+  uut : entity work.alias_extname_driving_signal
+    port map(
+      clk => clk
+    );
+
+  blk: block
+    alias counter_alias is << signal .alias_tb.uut.counter : unsigned(15 downto 0) >>;
+  begin
+    vector16 <= counter_alias;
+  end block;
+end architecture primary;
diff --git a/testsuite/gna/issue520/lrm.vhdl b/testsuite/gna/issue520/lrm.vhdl
new file mode 100644
index 000000000..954839177
--- /dev/null
+++ b/testsuite/gna/issue520/lrm.vhdl
@@ -0,0 +1,41 @@
+entity TOP is
+end entity TOP;
+
+architecture ARCH of TOP is
+  signal S1, S2, S3: BIT;
+  alias DONE_SIG is <<signal .TOP.DUT.DONE: BIT>>; -- Legal
+  constant DATA_WIDTH: INTEGER:= <<signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH;
+    -- Illegal, because .TOP.DUT.DATA has not yet been elaborated
+    --  when the expression is evaluated
+begin
+  P1: process ( DONE_SIG ) is -- Legal
+  begin
+    if DONE_SIG then -- Legal ...;
+    end if;
+  end process P1;
+
+  MONITOR: entity WORK.MY_MONITOR port map (DONE_SIG);
+  -- Illegal, because .TOP.DUT.DONE has not yet been elaborated
+  -- when the association element is elaborated
+  DUT: entity WORK.MY_DESIGN port map (s1, S2, S3);
+  MONITOR2: entity WORK.MY_MONITOR port map (DONE_SIG);
+  -- Legal, because .TOP.DUT.DONE has now been elaborated
+  B1: block
+    constant DATA_WIDTH: INTEGER := <<signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH
+    -- Legal, because .TOP.DUT.DATA has now been elaborated
+  begin
+  end block B1;
+  B2: block
+    constant C0: INTEGER := 6;
+    constant C1: INTEGER := <<constant .TOP.B3.C2: INTEGER>>;
+    -- Illegal, because .TOP.B3.C2 has not yet been elaborated
+  begin
+  end block B2;
+  B3: block
+    constant C2: INTEGER := <<constant .TOP.B2.C0: INTEGER>>; -- Legal
+  begin
+  end block B3;
+  -- Together, B2 and B3 are illegal, because they cannot be ordered
+  -- so that the objects are elaborated in the order .TOP.B2.C0,
+  -- then .TOP.B3.C2, and finally .TOP.B2.C1.
+end architecture ARCH;
diff --git a/testsuite/gna/issue520/testsuite.sh b/testsuite/gna/issue520/testsuite.sh
new file mode 100755
index 000000000..764d4c439
--- /dev/null
+++ b/testsuite/gna/issue520/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+$GHDL -s $GHDL_STD_FLAGS alias.vhdl
+
+clean
+
+echo "Test successful"