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-rw-r--r--testsuite/gna/issue339/test_bench.vhdl2
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/gna/issue339/test_bench.vhdl b/testsuite/gna/issue339/test_bench.vhdl
index 74344dac7..74d58e274 100644
--- a/testsuite/gna/issue339/test_bench.vhdl
+++ b/testsuite/gna/issue339/test_bench.vhdl
@@ -22,7 +22,7 @@ architecture bench of test_bench is
signal s_clk : std_logic := '1';
begin
- s_rst <= '1' after 50 ns;
+ s_rst <= '0' after 50 ns;
s_clk <= not s_clk after 10 ns;
write_result : process (s_rst, s_clk) is