10 files changed, 280 insertions, 0 deletions
diff --git a/testsuite/gna/issue328/repro.vhdl b/testsuite/gna/issue328/repro.vhdl
new file mode 100644
index 000000000..4de26cc47
--- /dev/null
+++ b/testsuite/gna/issue328/repro.vhdl
@@ -0,0 +1,39 @@
+entity repro is
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Test case architecture
+architecture func of repro is
+
+  signal s : std_logic := 'Z';
+
+  procedure write (signal s : inout std_logic) is
+  begin
+    null;
+  end write;
+begin
+  b: block
+    port (s1 : out std_logic := '0');
+    port map (s1 => s);
+  begin
+    process
+    begin
+      wait for 2 ns;
+      s1 <= 'Z';
+      wait;
+    end process;
+  end block;
+  
+  process
+  begin
+    write(s);
+    wait for 1 ns;
+    assert s = '0' severity failure;
+    wait for 2 ns;
+    assert s = 'Z' severity failure;
+    wait;
+  end process;
+end func;
diff --git a/testsuite/gna/issue328/repro2.vhdl b/testsuite/gna/issue328/repro2.vhdl
new file mode 100644
index 000000000..4f9e8ef13
--- /dev/null
+++ b/testsuite/gna/issue328/repro2.vhdl
@@ -0,0 +1,38 @@
+entity repro2 is
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Test case architecture
+architecture func of repro2 is
+
+  signal s : std_logic := 'Z';
+
+  procedure write (signal s : inout std_logic) is
+  begin
+    null;
+  end write;
+begin
+  b: block
+    port (s1 : out std_logic := '0');
+    port map (s1 => s);
+  begin
+    process
+    begin
+      s1 <= 'Z' after 2 ns;
+      wait;
+    end process;
+  end block;
+  
+  process
+  begin
+    write(s);
+    wait for 1 ns;
+    assert s = '0' severity failure;
+    wait for 2 ns;
+    assert s = 'Z' severity failure;
+    wait;
+  end process;
+end func;
diff --git a/testsuite/gna/issue328/repro_irqc.vhdl b/testsuite/gna/issue328/repro_irqc.vhdl
new file mode 100644
index 000000000..136b6942e
--- /dev/null
+++ b/testsuite/gna/issue328/repro_irqc.vhdl
@@ -0,0 +1,57 @@
+entity irqc_tb is
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Test case architecture
+architecture func of irqc_tb is
+
+  type t_sbi_if is record
+    cs      : std_logic;          -- to dut
+    addr    : unsigned;           -- to dut
+    rena    : std_logic;          -- to dut
+    wena    : std_logic;          -- to dut
+    wdata   : std_logic_vector;   -- to dut
+    ready   : std_logic;          -- from dut
+    rdata   : std_logic_vector;   -- from dut
+  end record;
+
+  function init_sbi_if_signals(
+    addr_width : natural;
+    data_width : natural
+    ) return t_sbi_if is
+    variable result : t_sbi_if( addr(addr_width - 1 downto 0), 
+                                wdata(data_width - 1 downto 0), 
+                                rdata(data_width - 1 downto 0));
+  begin
+    result.cs     := '0';
+    result.rena   := '0';
+    result.wena   := '0';
+    result.addr   := (others => '0');
+    result.wdata  := (others => '0');
+    result.ready  := 'Z';
+    result.rdata  := (others => 'Z');
+    return result;
+  end function;
+
+  signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
+
+  procedure write (signal s : inout t_sbi_if) is
+  begin
+    s.cs <= '1';
+  end write;
+begin
+  process
+  begin
+    write(sbi_if);
+    wait for 1 ns;
+    assert sbi_if.rdata = (7 downto 0 => 'Z');
+    assert sbi_if.addr = (2 downto 0 => '0');
+    assert sbi_if.wdata = (7 downto 0 => '0');
+    wait;
+  end process;
+
+  sbi_if.rdata <= (others => '0');
+end func;
diff --git a/testsuite/gna/issue328/t3.vhdl b/testsuite/gna/issue328/t3.vhdl
new file mode 100644
index 000000000..3825beab5
--- /dev/null
+++ b/testsuite/gna/issue328/t3.vhdl
@@ -0,0 +1,18 @@
+entity t3 is
+end t3;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of t3 is
+  signal s : std_logic;
+begin
+  b: block
+    port (p : out std_logic := '0');
+    port map (p => s);
+  begin
+  end block;
+
+  assert s = '0' severity failure;
+end behav;
diff --git a/testsuite/gna/issue328/t3b.vhdl b/testsuite/gna/issue328/t3b.vhdl
new file mode 100644
index 000000000..b6ed75a87
--- /dev/null
+++ b/testsuite/gna/issue328/t3b.vhdl
@@ -0,0 +1,23 @@
+entity t3b is
+end t3b;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of t3b is
+  signal s : std_logic := '0';
+begin
+  b: block
+    port (p : out std_logic);
+    port map (p => s);
+  begin
+  end block;
+
+  process
+  begin
+   wait for 1 ns;
+   assert s = 'U' severity failure;
+   wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue328/t4.vhdl b/testsuite/gna/issue328/t4.vhdl
new file mode 100644
index 000000000..6226ca664
--- /dev/null
+++ b/testsuite/gna/issue328/t4.vhdl
@@ -0,0 +1,24 @@
+entity t4 is
+end t4;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of t4 is
+  signal s : std_logic;
+begin
+  b: block
+    port (p : out std_logic := '0');
+    port map (p => s);
+  begin
+    process
+    begin
+      wait for 1 ns;
+      p <= '0';
+      wait;
+    end process;
+  end block;
+
+  assert s = '0' severity failure;
+end behav;
diff --git a/testsuite/gna/issue328/t5.vhdl b/testsuite/gna/issue328/t5.vhdl
new file mode 100644
index 000000000..042a64d8f
--- /dev/null
+++ b/testsuite/gna/issue328/t5.vhdl
@@ -0,0 +1,29 @@
+entity t5 is
+end t5;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of t5 is
+  signal s : std_logic := '0';
+begin
+  b: block
+    port (p : out std_logic := 'Z');
+    port map (p => s);
+  begin
+  end block;
+
+  b2: block
+    port (p : out std_logic := '1');
+    port map (p => s);
+  begin
+  end block;
+
+  process
+  begin
+   wait for 1 ns;
+   assert s = 'X' severity failure;
+   wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue328/t6.vhdl b/testsuite/gna/issue328/t6.vhdl
new file mode 100644
index 000000000..599c2a4b7
--- /dev/null
+++ b/testsuite/gna/issue328/t6.vhdl
@@ -0,0 +1,14 @@
+entity t6 is
+   port (s : inout natural := 6);
+end;
+
+architecture behav of t6 is
+begin
+  process
+  begin
+    s <= s + 1;
+    wait for 1 ns;
+    assert s = 7 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue328/testsuite.sh b/testsuite/gna/issue328/testsuite.sh
new file mode 100755
index 000000000..9491bb547
--- /dev/null
+++ b/testsuite/gna/issue328/testsuite.sh
@@ -0,0 +1,25 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze repro.vhdl
+elab_simulate repro
+
+analyze repro2.vhdl
+elab_simulate repro2
+
+analyze t3.vhdl
+elab_simulate t3
+
+analyze t3b.vhdl
+elab_simulate t3b
+
+analyze t4.vhdl
+elab_simulate t4
+
+analyze t6.vhdl
+elab_simulate t6
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue328/uncons1.vhdl b/testsuite/gna/issue328/uncons1.vhdl
new file mode 100644
index 000000000..5fe1c6df9
--- /dev/null
+++ b/testsuite/gna/issue328/uncons1.vhdl
@@ -0,0 +1,13 @@
+entity uncons1 is
+end;
+
+architecture behav of uncons1 is
+  signal s1, s2 : bit;
+begin
+  b : block
+     -- port (p : bit_vector := (others => '1'));
+     port (p : bit_vector := "01110");
+     port map (p(0) => s1, p(1) => s2);
+  begin
+  end block;
+end;