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-rw-r--r--testsuite/gna/issue317/repro1.vhdl23
1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/gna/issue317/repro1.vhdl b/testsuite/gna/issue317/repro1.vhdl
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+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+package sortnet_tb is
+ generic (
+ DATA_BITS : positive;
+ INPUTS : positive
+ );
+
+ subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0);
+ type T_DATA_VECTOR is array(natural range <>) of T_DATA;
+
+ type T_SCOREBOARD_DATA is record
+ Data : T_DATA_VECTOR(INPUTS - 1 downto 0);
+ end record;
+end sortnet_tb;
+
+entity repro1 is
+end repro1;
+
+architecture behav of repro1 is
+ package tb is new work.sortnet_tb generic map (3, 4);
+begin
+end behav;