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Diffstat (limited to 'testsuite/gna/issue1935/clock.vhdl')
-rw-r--r-- | testsuite/gna/issue1935/clock.vhdl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/gna/issue1935/clock.vhdl b/testsuite/gna/issue1935/clock.vhdl new file mode 100644 index 000000000..6fe2faef9 --- /dev/null +++ b/testsuite/gna/issue1935/clock.vhdl @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity clock is + port( + interval: in time; + EN : in std_logic; + CLK : out std_logic + ); + +end clock; + +architecture behave of clock is + +begin + + clock : process + begin + loop + exit when EN = '0'; + CLK <= not '1'; + wait for interval; + CLK <= not '0'; + wait for interval; + end loop; + + CLK <= '0'; + wait until EN = '1'; + end process; +end architecture; |