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-rw-r--r--testsuite/gna/issue1751/ent.vhdl18
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/gna/issue1751/ent.vhdl b/testsuite/gna/issue1751/ent.vhdl
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+++ b/testsuite/gna/issue1751/ent.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+end entity ent;
+
+architecture beh of ent is
+ signal sig_1 : std_logic;
+ alias a_sig_1 is sig_1;
+begin
+ process
+ begin
+ a_sig_1 <= force '1';
+ a_sig_1 <= release;
+ wait;
+ end process;
+end architecture beh;