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-rw-r--r--testsuite/gna/issue1672/test.vhdl22
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/gna/issue1672/test.vhdl b/testsuite/gna/issue1672/test.vhdl
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+++ b/testsuite/gna/issue1672/test.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+end entity;
+
+architecture a of test is
+
+ constant num_ports : positive := 4;
+ signal clock : std_logic := '0';
+
+begin
+
+ dut_inst : entity work.dut
+ generic map (
+ num_ports => num_ports
+ )
+ port map (
+ clocks => (others => clock)
+ );
+
+end architecture;