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-rw-r--r--testsuite/gna/bug051/tb2.vhdl17
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/gna/bug051/tb2.vhdl b/testsuite/gna/bug051/tb2.vhdl
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+++ b/testsuite/gna/bug051/tb2.vhdl
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+entity tb2 is
+end tb2;
+
+architecture behav of tb2 is
+ signal s : bit;
+ signal clk : bit;
+begin
+ -- psl default clock is (clk'event and clk = '1');
+ postponed assert always {s = '0'; s = '1'} severity failure;
+ process
+ begin
+ s <= '1';
+ wait for 0 ns;
+ s <= '0';
+ wait;
+ end process;
+end behav;