diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-expr.adb | 27 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 19 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.ads | 2 |
4 files changed, 24 insertions, 31 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 0e3b4cc46..c580fb613 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -1472,16 +1472,6 @@ package body Synth.Expr is end case; end Synth_Type_Conversion; - function Synth_Assoc_In (Syn_Inst : Synth_Instance_Acc; - Assoc : Node) return Value_Acc is - begin - if Get_Kind (Assoc) = Iir_Kind_Association_Element_By_Expression then - return Synth_Expression (Syn_Inst, Get_Actual (Assoc)); - else - Error_Kind ("synth_assoc_in", Assoc); - end if; - end Synth_Assoc_In; - procedure Error_Unknown_Operator (Imp : Node; Loc : Node) is begin if Get_Kind (Get_Parent (Imp)) = Iir_Kind_Package_Declaration @@ -1664,23 +1654,8 @@ package body Synth.Expr is when Iir_Kind_Function_Call => declare Imp : constant Node := Get_Implementation (Expr); - Clk : Net; - Edge : Net; begin - if Imp = Vhdl.Ieee.Std_Logic_1164.Rising_Edge then - Clk := Get_Net - (Synth_Assoc_In - (Syn_Inst, Get_Parameter_Association_Chain (Expr))); - Edge := Build_Edge (Build_Context, Clk); - return Create_Value_Net (Edge, Boolean_Type); - elsif Imp = Vhdl.Ieee.Std_Logic_1164.Falling_Edge then - Clk := Get_Net - (Synth_Assoc_In - (Syn_Inst, Get_Parameter_Association_Chain (Expr))); - Clk := Build_Monadic (Build_Context, Id_Not, Clk); - Edge := Build_Edge (Build_Context, Clk); - return Create_Value_Net (Edge, Boolean_Type); - elsif Get_Implicit_Definition (Imp) /= Iir_Predefined_None then + if Get_Implicit_Definition (Imp) /= Iir_Predefined_None then return Synth_Predefined_Function_Call (Syn_Inst, Expr); else return Synth_User_Function_Call (Syn_Inst, Expr); diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 0ff03d6a7..80504713e 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1092,6 +1092,25 @@ package body Synth.Oper is end if; case Def is + when Iir_Predefined_Ieee_1164_Rising_Edge => + declare + Clk : Net; + Edge : Net; + begin + Clk := Get_Net (Get_Value (Subprg_Inst, Param1)); + Edge := Build_Edge (Build_Context, Clk); + return Create_Value_Net (Edge, Boolean_Type); + end; + when Iir_Predefined_Ieee_1164_Falling_Edge => + declare + Clk : Net; + Edge : Net; + begin + Clk := Get_Net (Get_Value (Subprg_Inst, Param1)); + Clk := Build_Monadic (Build_Context, Id_Not, Clk); + Edge := Build_Edge (Build_Context, Clk); + return Create_Value_Net (Edge, Boolean_Type); + end; when Iir_Predefined_Ieee_1164_To_Bitvector => declare L : constant Value_Acc := Get_Value (Subprg_Inst, Param1); diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index d88a45ccb..50beaa554 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -120,6 +120,9 @@ package body Vhdl.Ieee.Std_Logic_1164 is is Error : exception; + Rising_Edge : Iir_Function_Declaration := Null_Iir; + Falling_Edge : Iir_Function_Declaration := Null_Iir; + Decl : Iir; Def : Iir; Predefined : Iir_Predefined_Functions; @@ -234,7 +237,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is case Get_Identifier (Decl) is when Name_Rising_Edge => Rising_Edge := Decl; - Predefined := Iir_Predefined_Ieee_1164_Falling_Edge; + Predefined := Iir_Predefined_Ieee_1164_Rising_Edge; when Name_Falling_Edge => Falling_Edge := Decl; Predefined := Iir_Predefined_Ieee_1164_Falling_Edge; @@ -333,7 +336,5 @@ package body Vhdl.Ieee.Std_Logic_1164 is Std_Logic_Vector_Type := Null_Iir; Std_Ulogic_0 := Null_Iir; Std_Ulogic_1 := Null_Iir; - Rising_Edge := Null_Iir; - Falling_Edge := Null_Iir; end Extract_Declarations; end Vhdl.Ieee.Std_Logic_1164; diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.ads b/src/vhdl/vhdl-ieee-std_logic_1164.ads index f5c92b5f1..487fb56ff 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.ads +++ b/src/vhdl/vhdl-ieee-std_logic_1164.ads @@ -26,8 +26,6 @@ package Vhdl.Ieee.Std_Logic_1164 is Std_Logic_Type : Iir_Enumeration_Subtype_Definition := Null_Iir; Std_Logic_Vector_Type : Iir_Array_Type_Definition := Null_Iir; Resolved : Iir_Function_Declaration := Null_Iir; - Rising_Edge : Iir_Function_Declaration := Null_Iir; - Falling_Edge : Iir_Function_Declaration := Null_Iir; -- Position of literals (D represents '-' ie dont-care). Std_Logic_U_Pos : constant := 0; |