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-rw-r--r--src/vhdl/simulate/simul-elaboration.adb6
-rw-r--r--src/vhdl/simulate/simul-execution.adb21
-rw-r--r--src/vhdl/simulate/simul-execution.ads7
3 files changed, 26 insertions, 8 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index 0eb6047c1..a6dc61ebf 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -848,11 +848,7 @@ package body Simul.Elaboration is
(Execute_Expression (Instance, Get_Left_Limit (Rc)),
Execute_Expression (Instance, Get_Right_Limit (Rc)),
Get_Direction (Rc));
- -- Check constraints.
- if not Is_Null_Range (Val) then
- Check_Constraints (Instance, Val.Left, Get_Type (Rc), Rc);
- Check_Constraints (Instance, Val.Right, Get_Type (Rc), Rc);
- end if;
+ Check_Range_Constraints (Instance, Val, Rc, Rc);
Instance.Objects (Range_Info.Slot) := Unshare (Val, Instance_Pool);
end Elaborate_Range_Expression;
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index b953d6d51..2eb890c54 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -657,6 +657,10 @@ package body Simul.Execution is
Eval_Right;
declare
+ -- Type of the index.
+ Idx_Type : constant Iir :=
+ Get_Nth_Element (Get_Index_Subtype_List (Res_Type), 0);
+
-- Array length of the result.
Len: Iir_Index32;
@@ -714,10 +718,10 @@ package body Simul.Execution is
-- Create the array result.
Result := Create_Array_Value (Len, 1);
Result.Bounds.D (1) := Create_Bounds_From_Length
- (Block,
- Get_Nth_Element (Get_Index_Subtype_List (Res_Type), 0),
- Len);
+ (Block, Idx_Type, Len);
end if;
+ Check_Range_Constraints
+ (Block, Result.Bounds.D (1), Idx_Type, Expr);
-- Fill the result: left.
case Func is
@@ -3868,6 +3872,17 @@ package body Simul.Execution is
Value := Ref_Value;
end Implicit_Array_Conversion;
+ procedure Check_Range_Constraints (Instance : Block_Instance_Acc;
+ Rng : Iir_Value_Literal_Acc;
+ Rng_Type : Iir;
+ Loc : Iir) is
+ begin
+ if not Is_Null_Range (Rng) then
+ Check_Constraints (Instance, Rng.Left, Get_Type (Rng_Type), Loc);
+ Check_Constraints (Instance, Rng.Right, Get_Type (Rng_Type), Loc);
+ end if;
+ end Check_Range_Constraints;
+
procedure Check_Array_Constraints
(Instance: Block_Instance_Acc;
Value: Iir_Value_Literal_Acc;
diff --git a/src/vhdl/simulate/simul-execution.ads b/src/vhdl/simulate/simul-execution.ads
index 66748b52a..566fa26db 100644
--- a/src/vhdl/simulate/simul-execution.ads
+++ b/src/vhdl/simulate/simul-execution.ads
@@ -139,6 +139,13 @@ package Simul.Execution is
(Instance: Block_Instance_Acc; Scope: Sim_Info_Acc)
return Block_Instance_Acc;
+ -- Check that bounds of RNG belong to RNG_TYPE (unless this is a null
+ -- range).
+ procedure Check_Range_Constraints (Instance : Block_Instance_Acc;
+ Rng : Iir_Value_Literal_Acc;
+ Rng_Type : Iir;
+ Loc : Iir);
+
-- Check VALUE follows the constraints of DEF.
-- INSTANCE,DEF is the definition of a subtype.
-- EXPR is just used in case of error to display the location