diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/elab-vhdl_expr.adb | 3 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_types.adb | 44 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 52 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 1 |
5 files changed, 55 insertions, 48 deletions
diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb index d897fee69..a920d2a8f 100644 --- a/src/synth/elab-vhdl_expr.adb +++ b/src/synth/elab-vhdl_expr.adb @@ -998,6 +998,7 @@ package body Elab.Vhdl_Expr is (Syn_Inst : Synth_Instance_Acc; Str : Node; Str_Typ : Type_Acc) return Valtyp is + pragma Unreferenced (Syn_Inst); pragma Assert (Get_Kind (Str) = Iir_Kind_String_Literal8); Id : constant String8_Id := Get_String8_Id (Str); @@ -1022,7 +1023,7 @@ package body Elab.Vhdl_Expr is raise Internal_Error; end case; - El_Type := Get_Subtype_Object (Syn_Inst, Get_Element_Subtype (Str_Type)); + El_Type := Get_Array_Element (Str_Typ); if El_Type.Kind in Type_Nets then Res_Type := Create_Vector_Type (Bounds, El_Type); else diff --git a/src/synth/elab-vhdl_types.adb b/src/synth/elab-vhdl_types.adb index 54bd3469b..7e9106f95 100644 --- a/src/synth/elab-vhdl_types.adb +++ b/src/synth/elab-vhdl_types.adb @@ -205,16 +205,28 @@ package body Elab.Vhdl_Types is El : Node; El_Type : Node; El_Typ : Type_Acc; + + Parent_Typ : Type_Acc; + Parent_Els : Rec_El_Array_Acc; begin Rec_Els := Create_Rec_El_Array (Iir_Index32 (Get_Nbr_Elements (El_List))); + if Is_Subtype then + Parent_Typ := Get_Subtype_Object (Syn_Inst, Get_Parent_Type (Def)); + Parent_Els := Parent_Typ.Rec; + end if; + for I in Flist_First .. Flist_Last (El_List) loop El := Get_Nth_Element (El_List, I); El_Type := Get_Type (El); if Is_Subtype then - Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); - El_Typ := Get_Subtype_Object (Syn_Inst, El_Type); + if Get_Kind (El) = Iir_Kind_Record_Element_Constraint then + El_Typ := Synth_Subtype_Indication_If_Anonymous + (Syn_Inst, El_Type); + else + El_Typ := Parent_Els.E (Iir_Index32 (I + 1)).Typ; + end if; else El_Typ := Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); @@ -414,47 +426,49 @@ package body Elab.Vhdl_Types is function Synth_Array_Subtype_Indication (Syn_Inst : Synth_Instance_Acc; Atype : Node) return Type_Acc is + Parent_Type : constant Node := Get_Parent_Type (Atype); El_Type : constant Node := Get_Element_Subtype (Atype); St_Indexes : constant Node_Flist := Get_Index_Subtype_List (Atype); - Ptype : Node; + Parent_Typ : constant Type_Acc := + Get_Subtype_Object (Syn_Inst, Parent_Type); St_El : Node; - Btyp : Type_Acc; - Etyp : Type_Acc; + El_Typ : Type_Acc; Bnds : Bound_Array_Acc; begin -- VHDL08 if Has_Element_Subtype_Indication (Atype) then -- This subtype has created a new anonymous subtype for the -- element. - Synth_Subtype_Indication (Syn_Inst, El_Type); + El_Typ := Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); + else + El_Typ := Get_Array_Element (Parent_Typ); end if; if not Get_Index_Constraint_Flag (Atype) then - Ptype := Get_Type (Get_Subtype_Type_Mark (Atype)); - if Get_Element_Subtype (Ptype) = Get_Element_Subtype (Atype) then + if Get_Element_Subtype (Parent_Type) + = Get_Element_Subtype (Atype) + then -- That's an alias. -- FIXME: maybe a resolution function was added? -- FIXME: also handle resolution added in element subtype. - return Get_Subtype_Object (Syn_Inst, Ptype); + return Parent_Typ; end if; end if; - Btyp := Get_Subtype_Object (Syn_Inst, Get_Base_Type (Atype)); - case Btyp.Kind is + case Parent_Typ.Kind is when Type_Unbounded_Vector => if Get_Index_Constraint_Flag (Atype) then St_El := Get_Index_Type (St_Indexes, 0); return Create_Vector_Type - (Synth_Bounds_From_Range (Syn_Inst, St_El), Btyp.Uvec_El); + (Synth_Bounds_From_Range (Syn_Inst, St_El), El_Typ); else -- An alias. -- Handle vhdl08 definition of std_logic_vector from -- std_ulogic_vector. - return Btyp; + return Parent_Typ; end if; when Type_Unbounded_Array => -- FIXME: partially constrained arrays, subtype in indexes... - Etyp := Get_Subtype_Object (Syn_Inst, El_Type); if Get_Index_Constraint_Flag (Atype) then Bnds := Create_Bound_Array (Dim_Type (Get_Nbr_Elements (St_Indexes))); @@ -463,7 +477,7 @@ package body Elab.Vhdl_Types is Bnds.D (Dim_Type (I + 1)) := Synth_Bounds_From_Range (Syn_Inst, St_El); end loop; - return Create_Array_Type (Bnds, Etyp); + return Create_Array_Type (Bnds, El_Typ); else raise Internal_Error; end if; diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 834f1de47..0ad0b4420 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -1661,6 +1661,7 @@ package body Synth.Vhdl_Expr is (Syn_Inst : Synth_Instance_Acc; Str : Node; Str_Typ : Type_Acc) return Valtyp is + pragma Unreferenced (Syn_Inst); pragma Assert (Get_Kind (Str) = Iir_Kind_String_Literal8); Id : constant String8_Id := Get_String8_Id (Str); @@ -1685,7 +1686,7 @@ package body Synth.Vhdl_Expr is raise Internal_Error; end case; - El_Type := Get_Subtype_Object (Syn_Inst, Get_Element_Subtype (Str_Type)); + El_Type := Get_Array_Element (Str_Typ); if El_Type.Kind in Type_Nets then Res_Type := Create_Vector_Type (Bounds, El_Type); else diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 9fc9788bf..7e1663e9a 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -324,29 +324,34 @@ package body Vhdl.Annotations is end if; when Iir_Kind_Array_Type_Definition => - El := Get_Element_Subtype (Def); - Annotate_Anonymous_Type_Definition (Block_Info, El); if Flag_Synthesis then + -- Create an annotation for the element type, as it can be + -- referenced by the implicit concat function definition for + -- concatenation with element. + El := Get_Element_Subtype (Def); + Annotate_Anonymous_Type_Definition (Block_Info, El); + + -- Then for the array. Create_Object_Info (Block_Info, Def, Kind_Type); end if; when Iir_Kind_Array_Subtype_Definition => - if Get_Array_Element_Constraint (Def) /= Null_Node - or else - (Get_Resolution_Indication (Def) /= Null_Node - and then - (Get_Kind (Get_Resolution_Indication (Def)) - = Iir_Kind_Array_Element_Resolution)) - then - -- This subtype has created a new anonymous subtype for the - -- element. - El := Get_Element_Subtype (Def); - Annotate_Type_Definition (Block_Info, El); - end if; if Flag_Synthesis then -- For the bounds. Create_Object_Info (Block_Info, Def, Kind_Type); else + if Get_Array_Element_Constraint (Def) /= Null_Node + or else + (Get_Resolution_Indication (Def) /= Null_Node + and then + (Get_Kind (Get_Resolution_Indication (Def)) + = Iir_Kind_Array_Element_Resolution)) + then + -- This subtype has created a new anonymous subtype for the + -- element. + El := Get_Element_Subtype (Def); + Annotate_Type_Definition (Block_Info, El); + end if; declare List : constant Iir_Flist := Get_Index_Subtype_List (Def); begin @@ -378,23 +383,8 @@ package body Vhdl.Annotations is when Iir_Kind_Record_Subtype_Definition => if Flag_Synthesis then - declare - List : constant Iir_Flist := - Get_Elements_Declaration_List (Def); - El : Iir; - El_Type : Iir; - begin - for I in Flist_First .. Flist_Last (List) loop - El := Get_Nth_Element (List, I); - if Get_Subtype_Indication (El) /= Null_Iir then - El_Type := Get_Type (El); - Annotate_Anonymous_Type_Definition - (Block_Info, El_Type); - end if; - end loop; - -- For the offsets. - Create_Object_Info (Block_Info, Def, Kind_Type); - end; + -- For the offsets. + Create_Object_Info (Block_Info, Def, Kind_Type); end if; when Iir_Kind_Access_Type_Definition => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index aac961bb6..c419cc599 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -2928,6 +2928,7 @@ package Vhdl.Nodes is -- of the tree (ownership). -- Get/Set_Owned_Elements_Chain (Field6) -- + -- Chain of either element_declaration or record_element_constraint. -- Get/Set_Elements_Declaration_List (Field1) -- -- Get/Set_Subtype_Type_Mark (Field2) |