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-rw-r--r--src/synth/elab-vhdl_insts.adb2
-rw-r--r--src/synth/synth-vhdl_expr.adb3
-rw-r--r--src/synth/synth-vhdl_insts.adb40
-rw-r--r--src/synth/synth-vhdl_stmts.adb24
-rw-r--r--src/synth/synth-vhdl_stmts.ads11
5 files changed, 40 insertions, 40 deletions
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index dc2dbbeb1..a24d62713 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -102,7 +102,7 @@ package body Elab.Vhdl_Insts is
Dyn : Dyn_Name;
begin
Synth_Assignment_Prefix
- (Syn_Inst, Sub_Inst, Formal,
+ (Syn_Inst, Formal,
Formal_Base, Formal_Typ, Formal_Offs, Dyn);
pragma Assert (Dyn = No_Dyn_Name);
end;
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index 23665e8c1..d5a0e98fa 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -2267,8 +2267,7 @@ package body Synth.Vhdl_Expr is
Dyn : Dyn_Name;
begin
- Synth_Assignment_Prefix
- (Syn_Inst, Syn_Inst, Expr, Base, Typ, Off, Dyn);
+ Synth_Assignment_Prefix (Syn_Inst, Expr, Base, Typ, Off, Dyn);
if Base = No_Valtyp then
-- Propagate error.
return No_Valtyp;
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb
index 3e7e59f6c..addd5a9da 100644
--- a/src/synth/synth-vhdl_insts.adb
+++ b/src/synth/synth-vhdl_insts.adb
@@ -36,6 +36,7 @@ with Netlists.Folds;
with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
with Elab.Vhdl_Values; use Elab.Vhdl_Values;
+with Elab.Vhdl_Types;
with Vhdl.Utils; use Vhdl.Utils;
with Vhdl.Errors;
@@ -715,12 +716,13 @@ package body Synth.Vhdl_Insts is
end Sort_Value_Offset;
function Synth_Individual_Input_Assoc (Syn_Inst : Synth_Instance_Acc;
- Assoc : Node;
- Inter_Inst : Synth_Instance_Acc)
- return Net
+ Inter_Typ : Type_Acc;
+ Assoc : Node) return Net
is
+ pragma Unreferenced (Inter_Typ);
use Netlists.Concats;
Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
+ Formal_Typ : Type_Acc;
Iassoc : Node;
V : Valtyp;
Typ : Type_Acc;
@@ -728,21 +730,22 @@ package body Synth.Vhdl_Insts is
Concat : Concat_Type;
N_Off : Uns32;
N : Net;
- Base : Valtyp;
Offs : Value_Offsets;
- Dyn : Dyn_Name;
begin
Value_Offset_Tables.Init (Els, 16);
+ -- FIXME: should it be unshared ?
+ Formal_Typ := Elab.Vhdl_Types.Synth_Subtype_Indication
+ (Syn_Inst, Get_Actual_Type (Assoc));
+
Iassoc := Get_Chain (Assoc);
while Iassoc /= Null_Node
and then not Get_Whole_Association_Flag (Iassoc)
loop
-- For each individual assoc:
-- 1. compute type and offset
- Synth_Assignment_Prefix
- (Syn_Inst, Inter_Inst, Get_Formal (Iassoc), Base, Typ, Offs, Dyn);
- pragma Assert (Dyn = No_Dyn_Name);
+ Synth_Individual_Formal
+ (Syn_Inst, Formal_Typ, Get_Formal (Iassoc), Typ, Offs);
-- 2. synth expression
V := Synth_Single_Input_Assoc
@@ -754,8 +757,6 @@ package body Synth.Vhdl_Insts is
Iassoc := Get_Chain (Iassoc);
end loop;
- pragma Unreferenced (Base);
-
-- Then:
-- 1. sort table by offset
Sort_Value_Offset (Els);
@@ -799,7 +800,7 @@ package body Synth.Vhdl_Insts is
(Syn_Inst, Inter_Typ, Syn_Inst, Get_Actual (Assoc), Assoc);
when Iir_Kind_Association_Element_By_Individual =>
Res_Net := Synth_Individual_Input_Assoc
- (Syn_Inst, Assoc, Inter_Inst);
+ (Syn_Inst, Inter_Typ, Assoc);
Release_Expr_Pool (Marker);
return Res_Net;
end case;
@@ -815,8 +816,8 @@ package body Synth.Vhdl_Insts is
procedure Synth_Individual_Output_Assoc (Outp : Net;
Syn_Inst : Synth_Instance_Acc;
- Assoc : Node;
- Inter_Inst : Synth_Instance_Acc)
+ Inter_Typ : Type_Acc;
+ Assoc : Node)
is
Marker : Mark_Type;
Iassoc : Node;
@@ -824,8 +825,6 @@ package body Synth.Vhdl_Insts is
Typ : Type_Acc;
O : Net;
Port : Net;
- Base : Valtyp;
- Dyn : Dyn_Name;
Offs : Value_Offsets;
begin
Mark_Expr_Pool (Marker);
@@ -839,9 +838,8 @@ package body Synth.Vhdl_Insts is
loop
-- For each individual assoc:
-- 1. compute type and offset
- Synth_Assignment_Prefix
- (Syn_Inst, Inter_Inst, Get_Formal (Iassoc), Base, Typ, Offs, Dyn);
- pragma Assert (Dyn = No_Dyn_Name);
+ Synth_Individual_Formal
+ (Syn_Inst, Inter_Typ, Get_Formal (Iassoc), Typ, Offs);
-- 2. Extract the value.
O := Build_Extract (Get_Build (Syn_Inst), Port, Offs.Net_Off, Typ.W);
@@ -868,6 +866,8 @@ package body Synth.Vhdl_Insts is
Port : Net;
O : Valtyp;
begin
+ Formal_Typ := Get_Value (Inter_Inst, Inter).Typ;
+
case Get_Kind (Assoc) is
when Iir_Kind_Association_Element_Open =>
-- Not connected.
@@ -876,12 +876,10 @@ package body Synth.Vhdl_Insts is
Actual := Get_Actual (Assoc);
when others =>
Synth_Individual_Output_Assoc
- (Outp, Syn_Inst, Assoc, Inter_Inst);
+ (Outp, Syn_Inst, Formal_Typ, Assoc);
return;
end case;
- Formal_Typ := Get_Value (Inter_Inst, Inter).Typ;
-
Mark_Expr_Pool (Marker);
-- Create a port gate (so that is has a name).
Port := Builders.Build_Port (Get_Build (Syn_Inst), Outp);
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 977741469..a0870cdd1 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -222,7 +222,6 @@ package body Synth.Vhdl_Stmts is
end Synth_Assignment_Prefix_Slice_Name;
procedure Synth_Assignment_Prefix (Syn_Inst : Synth_Instance_Acc;
- Inter_Inst : Synth_Instance_Acc;
Pfx : Node;
Dest_Base : out Valtyp;
Dest_Typ : out Type_Acc;
@@ -251,13 +250,13 @@ package body Synth.Vhdl_Stmts is
| Iir_Kind_Selected_Name
| Iir_Kind_Attribute_Name =>
Synth_Assignment_Prefix
- (Syn_Inst, Inter_Inst, Get_Named_Entity (Pfx),
+ (Syn_Inst, Get_Named_Entity (Pfx),
Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
when Iir_Kind_Interface_Signal_Declaration
| Iir_Kind_Interface_Variable_Declaration
| Iir_Kind_Interface_Constant_Declaration
| Iir_Kind_Interface_File_Declaration =>
- Assign_Base (Inter_Inst);
+ Assign_Base (Syn_Inst);
when Iir_Kind_Variable_Declaration
| Iir_Kind_Signal_Declaration
| Iir_Kind_Guard_Signal_Declaration
@@ -274,21 +273,21 @@ package body Synth.Vhdl_Stmts is
when Iir_Kind_Indexed_Name =>
Synth_Assignment_Prefix
- (Syn_Inst, Inter_Inst, Get_Prefix (Pfx),
+ (Syn_Inst, Get_Prefix (Pfx),
Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
Synth_Assignment_Prefix_Indexed_Name
(Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
when Iir_Kind_Selected_Element =>
Synth_Assignment_Prefix
- (Syn_Inst, Inter_Inst, Get_Prefix (Pfx),
+ (Syn_Inst, Get_Prefix (Pfx),
Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
Synth_Assignment_Prefix_Selected_Name
(Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
when Iir_Kind_Slice_Name =>
Synth_Assignment_Prefix
- (Syn_Inst, Inter_Inst, Get_Prefix (Pfx),
+ (Syn_Inst, Get_Prefix (Pfx),
Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
Synth_Assignment_Prefix_Slice_Name
(Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn);
@@ -338,7 +337,7 @@ package body Synth.Vhdl_Stmts is
Dyn : Dyn_Name;
begin
Synth_Assignment_Prefix
- (Syn_Inst, Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dyn);
+ (Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dyn);
pragma Assert (Dyn = No_Dyn_Name);
end Synth_Assignment_Prefix;
@@ -471,7 +470,7 @@ package body Synth.Vhdl_Stmts is
Dyn : Dyn_Name;
begin
Synth_Assignment_Prefix
- (Syn_Inst, Syn_Inst, Target, Base, Typ, Off, Dyn);
+ (Syn_Inst, Target, Base, Typ, Off, Dyn);
return To_Target_Info (Base, Typ, Off, Dyn);
end;
when others =>
@@ -2129,7 +2128,7 @@ package body Synth.Vhdl_Stmts is
end Copy_Unbounded_Type;
procedure Synth_Individual_Formal (Syn_Inst : Synth_Instance_Acc;
- Formal : Valtyp;
+ Formal : Type_Acc;
Pfx : Node;
Dest_Typ : out Type_Acc;
Dest_Off : out Value_Offsets) is
@@ -2143,7 +2142,7 @@ package body Synth.Vhdl_Stmts is
| Iir_Kind_Interface_Variable_Declaration
| Iir_Kind_Interface_Constant_Declaration
| Iir_Kind_Interface_File_Declaration =>
- Dest_Typ := Formal.Typ;
+ Dest_Typ := Formal;
Dest_Off := No_Value_Offsets;
when Iir_Kind_Indexed_Name =>
@@ -2238,7 +2237,7 @@ package body Synth.Vhdl_Stmts is
Cb_Val : Valtyp;
begin
Synth_Individual_Formal
- (Caller_Inst, Res, Formal, Form_Typ, Form_Off);
+ (Caller_Inst, Formal_Typ, Formal, Form_Typ, Form_Off);
if Inter_Kind = Iir_Kind_Interface_Constant_Declaration then
Act_Base := Synth_Expression_With_Type
@@ -2248,8 +2247,7 @@ package body Synth.Vhdl_Stmts is
Act_Dyn := No_Dyn_Name;
else
Synth_Assignment_Prefix
- (Caller_Inst, Caller_Inst,
- Actual, Act_Base, Act_Typ, Act_Off, Act_Dyn);
+ (Caller_Inst, Actual, Act_Base, Act_Typ, Act_Off, Act_Dyn);
end if;
if Get_Actual_Conversion (Assoc) /= Null_Node then
-- TODO
diff --git a/src/synth/synth-vhdl_stmts.ads b/src/synth/synth-vhdl_stmts.ads
index b6cc72fce..120a0741e 100644
--- a/src/synth/synth-vhdl_stmts.ads
+++ b/src/synth/synth-vhdl_stmts.ads
@@ -76,10 +76,7 @@ package Synth.Vhdl_Stmts is
-- DEST_TYP is the type of the result.
-- DEST_OFF is the offset, within DEST_DYN.
-- DEST_DYN is set (Voff field set) when there is a non-static index.
- -- SYN_INST is used for all parts except when PFX is an interface. In the
- -- latter, INTER_INST is used.
procedure Synth_Assignment_Prefix (Syn_Inst : Synth_Instance_Acc;
- Inter_Inst : Synth_Instance_Acc;
Pfx : Node;
Dest_Base : out Valtyp;
Dest_Typ : out Type_Acc;
@@ -93,6 +90,14 @@ package Synth.Vhdl_Stmts is
Dest_Typ : out Type_Acc;
Dest_Off : out Value_Offsets);
+ -- Likewise but for a formal name.
+ procedure Synth_Individual_Formal (Syn_Inst : Synth_Instance_Acc;
+ Formal : Type_Acc;
+ Pfx : Node;
+ Dest_Typ : out Type_Acc;
+ Dest_Off : out Value_Offsets);
+
+
procedure Synth_Assignment (Syn_Inst : Synth_Instance_Acc;
Target : Node;
Val : Valtyp;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 07:11:26 +0000