diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-static_oper.adb | 26 | ||||
| -rw-r--r-- | src/vhdl/vhdl-evaluation.adb | 6 |
2 files changed, 29 insertions, 3 deletions
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 504e49c04..d5dc9159a 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -41,6 +41,12 @@ package body Synth.Static_Oper is -- (math library) on unix systems. pragma Linker_Options ("-lm"); + type Tf_Table_2d is array (Boolean, Boolean) of Boolean; + + Tf_2d_And : constant Tf_Table_2d := + (False => (others => False), + True => (True => True, False => False)); + function Create_Res_Bound (Prev : Type_Acc) return Type_Acc is begin if Prev.Vbound.Dir = Dir_Downto @@ -78,6 +84,21 @@ package body Synth.Static_Oper is return Res; end Synth_Vector_Dyadic; + function Synth_Tf_Array_Element (El, Arr : Memtyp; + Op : Tf_Table_2d) return Memtyp + is + Res : Memtyp; + Ve, Va : Boolean; + begin + Res := Create_Memory (Arr.Typ); + Ve := Boolean'Val (Read_U8 (El.Mem)); + for I in 1 .. Arr.Typ.Sz loop + Va := Boolean'Val (Read_U8 (Arr.Mem + (I - 1))); + Write_U8 (Res.Mem + (I - 1), Boolean'Pos (Op (Ve, Va))); + end loop; + return Res; + end Synth_Tf_Array_Element; + function Get_Static_Ulogic (Op : Memtyp) return Std_Ulogic is begin pragma Assert (Op.Typ.Kind = Type_Logic); @@ -391,6 +412,11 @@ package body Synth.Static_Oper is end; end if; + when Iir_Predefined_TF_Element_Array_And => + return Synth_Tf_Array_Element (Left, Right, Tf_2d_And); + when Iir_Predefined_TF_Array_Element_And => + return Synth_Tf_Array_Element (Right, Left, Tf_2d_And); + when Iir_Predefined_Ieee_1164_Vector_And | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn => diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index 1c2a8c8f2..cfbb231c6 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -1003,7 +1003,8 @@ package body Vhdl.Evaluation is Res_Type := Convert_Typ_To_Node (Mt.Typ, Btype, Orig); return Convert_Vect_To_Simple_Aggregate (Mt, Res_Type, Orig); - when Type_Logic => + when Type_Logic + | Type_Bit => return Convert_Discrete_To_Node (Read_Discrete (Mt), Btype, Orig); when others => @@ -2569,8 +2570,7 @@ package body Vhdl.Evaluation is | Iir_Predefined_TF_Element_Array_Xor | Iir_Predefined_TF_Array_Element_Xnor | Iir_Predefined_TF_Element_Array_Xnor => - -- TODO - raise Internal_Error; + return Eval_Ieee_Operator (Orig, Imp, Left, Right); when Iir_Predefined_TF_Reduction_And | Iir_Predefined_TF_Reduction_Or |