diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-oper.adb | 15 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 77 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 26 |
4 files changed, 117 insertions, 3 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 1c8560074..c78515e57 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -831,7 +831,10 @@ package body Synth.Oper is | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv => + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns => -- "+" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int @@ -859,7 +862,10 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log => + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int @@ -1132,7 +1138,8 @@ package body Synth.Oper is -- ">" (Natural, Unsigned) [resize] return Synth_Compare_Nat_Uns (Id_Ugt, Expr_Typ); when Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Sgn - | Iir_Predefined_Ieee_Numeric_Std_Match_Gt_Sgn_Sgn => + | Iir_Predefined_Ieee_Numeric_Std_Match_Gt_Sgn_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Sgn => -- ">" (Signed, Signed) [resize] return Synth_Compare_Sgn_Sgn (Id_Sgt, Expr_Typ); when Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Int @@ -1507,6 +1514,8 @@ package body Synth.Oper is raise Internal_Error; end if; return Create_Value_Net (Get_Net (L), Create_Res_Bound (L)); + when Iir_Predefined_Ieee_1164_To_Bit => + return Create_Value_Net (Get_Net (L), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => return Synth_Conv_Vector (False); diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 6947cb612..58fe96229 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -300,6 +300,8 @@ package body Vhdl.Ieee.Std_Logic_1164 is -- parameter, clear the flag to allow more optimizations. Set_Has_Active_Flag (Get_Interface_Declaration_Chain (Decl), False); + when Name_To_Bit => + Predefined := Iir_Predefined_Ieee_1164_To_Bit; when Name_To_Bitvector => Predefined := Iir_Predefined_Ieee_1164_To_Bitvector; when Name_To_Stdulogic => diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index c1d7caccf..ded3ff0c3 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -173,6 +173,80 @@ package body Vhdl.Ieee.Std_Logic_Arith is others => (others => Iir_Predefined_None))); + Sub_Patterns : constant Bin_Pattern_Type := + (Type_Slv => + (Type_Unsigned => + (Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv, + Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv, + Type_Int => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv, + Type_Log => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv), + Type_Signed => + (Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv, + Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv, + Type_Int => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv, + Type_Log => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv), + Type_Int => + (Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv, + Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv, + others => Iir_Predefined_None), + Type_Log => + (Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv, + Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv, + others => Iir_Predefined_None)), + Type_Signed => + (Type_Signed => + (Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn, + Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn, + Type_Int => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn, + Type_Log => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn), + Type_Unsigned => + (Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn, + others => Iir_Predefined_None), + Type_Int => + (Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn, + others => Iir_Predefined_None), + Type_Log => + (Type_Signed => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn, + others => Iir_Predefined_None)), + Type_Unsigned => + (Type_Unsigned => + (Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns, + Type_Int => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns, + Type_Log => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns, + others => Iir_Predefined_None), + Type_Int => + (Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns, + others => Iir_Predefined_None), + Type_Log => + (Type_Unsigned => + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns, + others => Iir_Predefined_None), + others => + (others => Iir_Predefined_None))); + Lt_Patterns : constant Cmp_Pattern_Type := (Type_Unsigned => (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Uns, @@ -378,6 +452,9 @@ package body Vhdl.Ieee.Std_Logic_Arith is when Name_Op_Plus => Classify_Arg (Decl, Res_Kind); Def := Handle_Bin (Add_Patterns); + when Name_Op_Minus => + Classify_Arg (Decl, Res_Kind); + Def := Handle_Bin (Sub_Patterns); when Name_Op_Mul => Classify_Arg (Decl, Res_Kind); Def := Handle_Bin (Mul_Patterns); diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 8b9345d00..323587548 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5822,6 +5822,32 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv, Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn, + + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Sgn, |