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-rw-r--r--src/vhdl/parse.adb1
-rw-r--r--src/vhdl/sem.adb8
-rw-r--r--src/vhdl/translate/trans-chap2.adb59
-rw-r--r--src/vhdl/translate/trans-chap2.ads1
-rw-r--r--src/vhdl/translate/trans-chap4.adb6
5 files changed, 47 insertions, 28 deletions
diff --git a/src/vhdl/parse.adb b/src/vhdl/parse.adb
index bb623ea09..4f3dcd658 100644
--- a/src/vhdl/parse.adb
+++ b/src/vhdl/parse.adb
@@ -8286,6 +8286,7 @@ package body Parse is
Res : Iir;
begin
Res := Create_Iir (Iir_Kind_Package_Header);
+ Set_Location (Res);
Parse_Generic_Clause (Res);
if Current_Token = Tok_Generic then
diff --git a/src/vhdl/sem.adb b/src/vhdl/sem.adb
index a1bc4dc04..8187ffd36 100644
--- a/src/vhdl/sem.adb
+++ b/src/vhdl/sem.adb
@@ -390,7 +390,8 @@ package body Sem is
Miss := Missing_Allowed;
when Iir_Kind_Block_Header =>
Miss := Missing_Generic;
- when Iir_Kind_Package_Instantiation_Declaration =>
+ when Iir_Kind_Package_Instantiation_Declaration
+ | Iir_Kind_Package_Header =>
-- LRM08 4.9
-- Each formal generic (or member thereof) shall be associated
-- at most once.
@@ -2606,8 +2607,9 @@ package body Sem is
Sem_Interface_Chain
(Get_Generic_Chain (Header), Generic_Interface_List);
if Get_Generic_Map_Aspect_Chain (Header) /= Null_Iir then
- -- FIXME: todo
- raise Internal_Error;
+ if not Sem_Generic_Association_Chain (Header, Header) then
+ null;
+ end if;
end if;
end if;
diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index daa9d4e13..1ce10e22b 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -37,8 +37,6 @@ package body Trans.Chap2 is
use Trans.Subprgs;
use Trans.Helpers;
- procedure Elab_Package (Spec : Iir_Package_Declaration);
-
type Name_String_Xlat_Array is array (Name_Id range <>) of String (1 .. 4);
-- Ortho function names are only composed of [A-Za-z0-9_]. For VHDL
@@ -798,6 +796,9 @@ package body Trans.Chap2 is
(Info.Package_Body_Scope'Access, Info.Package_Body_Ptr_Type,
Wki_Instance, Prev_Subprg_Instance);
else
+ if Header /= Null_Iir then
+ Chap4.Translate_Generic_Chain (Header);
+ end if;
Chap4.Translate_Declaration_Chain (Decl);
if not Is_Nested then
Info.Package_Elab_Var := Create_Var
@@ -950,38 +951,50 @@ package body Trans.Chap2 is
procedure Elab_Package (Spec : Iir_Package_Declaration)
is
+ Is_Nested : constant Boolean := Is_Nested_Package (Spec);
Info : constant Ortho_Info_Acc := Get_Info (Spec);
Final : Boolean;
Constr : O_Assoc_List;
pragma Unreferenced (Final);
begin
- Start_Subprogram_Body (Info.Package_Elab_Spec_Subprg);
- Push_Local_Factory;
- Subprgs.Start_Subprg_Instance_Use (Info.Package_Elab_Spec_Instance);
+ if not Is_Nested then
+ Start_Subprogram_Body (Info.Package_Elab_Spec_Subprg);
+ Push_Local_Factory;
+ Subprgs.Start_Subprg_Instance_Use (Info.Package_Elab_Spec_Instance);
- Elab_Dependence (Get_Design_Unit (Spec));
+ Elab_Dependence (Get_Design_Unit (Spec));
- if not Is_Uninstantiated_Package (Spec)
- and then Get_Kind (Get_Parent (Spec)) = Iir_Kind_Design_Unit
- then
- -- Register the top level package. This is done dynamically, as
- -- we know only during elaboration that the design depends on a
- -- package (a package maybe referenced by an entity which is never
- -- instantiated due to generate statements).
- Start_Association (Constr, Ghdl_Rti_Add_Package);
- New_Association
- (Constr,
- New_Lit (Rtis.New_Rti_Address (Info.Package_Rti_Const)));
- New_Procedure_Call (Constr);
+ if not Is_Uninstantiated_Package (Spec)
+ and then Get_Kind (Get_Parent (Spec)) = Iir_Kind_Design_Unit
+ then
+ -- Register the top level package. This is done dynamically, as
+ -- we know only during elaboration that the design depends on a
+ -- package (a package maybe referenced by an entity which is never
+ -- instantiated due to generate statements).
+ Start_Association (Constr, Ghdl_Rti_Add_Package);
+ New_Association
+ (Constr,
+ New_Lit (Rtis.New_Rti_Address (Info.Package_Rti_Const)));
+ New_Procedure_Call (Constr);
+ end if;
+
+ Open_Temp;
end if;
- Open_Temp;
+ if Is_Generic_Mapped_Package (Spec) then
+ Chap5.Elab_Generic_Map_Aspect
+ (Get_Package_Header (Spec), (Info.Package_Spec_Scope'Access,
+ Info.Package_Spec_Scope));
+ end if;
Chap4.Elab_Declaration_Chain (Spec, Final);
- Close_Temp;
- Subprgs.Finish_Subprg_Instance_Use (Info.Package_Elab_Spec_Instance);
- Pop_Local_Factory;
- Finish_Subprogram_Body;
+ if not Is_Nested then
+ Close_Temp;
+
+ Subprgs.Finish_Subprg_Instance_Use (Info.Package_Elab_Spec_Instance);
+ Pop_Local_Factory;
+ Finish_Subprogram_Body;
+ end if;
end Elab_Package;
procedure Elab_Package_Body (Spec : Iir_Package_Declaration; Bod : Iir)
diff --git a/src/vhdl/translate/trans-chap2.ads b/src/vhdl/translate/trans-chap2.ads
index 21e0e2ae6..74247d6e1 100644
--- a/src/vhdl/translate/trans-chap2.ads
+++ b/src/vhdl/translate/trans-chap2.ads
@@ -35,6 +35,7 @@ package Trans.Chap2 is
procedure Translate_Package_Body (Bod : Iir_Package_Body);
procedure Translate_Package_Instantiation_Declaration (Inst : Iir);
+ procedure Elab_Package (Spec : Iir_Package_Declaration);
procedure Elab_Package_Body (Spec : Iir_Package_Declaration; Bod : Iir);
procedure Elab_Package_Instantiation_Declaration (Inst : Iir);
diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb
index c69eb63b5..a61246c57 100644
--- a/src/vhdl/translate/trans-chap4.adb
+++ b/src/vhdl/translate/trans-chap4.adb
@@ -2458,8 +2458,10 @@ package body Trans.Chap4 is
| Iir_Kind_Group_Declaration =>
null;
- when Iir_Kind_Package_Declaration
- | Iir_Kind_Package_Body =>
+ when Iir_Kind_Package_Declaration =>
+ Chap2.Elab_Package (Decl);
+ -- FIXME: finalizer
+ when Iir_Kind_Package_Body =>
declare
Nested_Final : Boolean;
begin
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