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-rw-r--r--src/vhdl/vhdl-ieee-std_logic_1164.adb6
-rw-r--r--src/vhdl/vhdl-nodes.ads3
2 files changed, 9 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 431b5bf6a..9c123d16a 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -271,6 +271,9 @@ package body Vhdl.Ieee.Std_Logic_1164 is
when Name_Op_Condition =>
Predefined :=
Iir_Predefined_Ieee_1164_Condition_Operator;
+ when Name_Is_X =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Scalar_Is_X;
when others =>
Predefined := Iir_Predefined_None;
end case;
@@ -301,6 +304,9 @@ package body Vhdl.Ieee.Std_Logic_1164 is
when Name_Or =>
Predefined :=
Iir_Predefined_Ieee_1164_Vector_Or_Reduce;
+ when Name_Is_X =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Scalar_Is_X;
when others =>
Predefined := Iir_Predefined_None;
end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 1f65efb0f..688c30555 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4920,6 +4920,9 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_1164_To_Bitvector,
+ Iir_Predefined_Ieee_1164_Vector_Is_X,
+ Iir_Predefined_Ieee_1164_Scalar_Is_X,
+
Iir_Predefined_Ieee_1164_Rising_Edge,
Iir_Predefined_Ieee_1164_Falling_Edge,