1 files changed, 10 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index c73681b7c..5b3248aef 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -505,6 +505,16 @@ package body Vhdl.Sem_Psl is
       case Get_Kind (Prop) is
          when N_Braced_SERE =>
             return Sem_Sequence (Prop);
+         when N_Star_Repeat_Seq
+            | N_Equal_Repeat_Seq
+            | N_Plus_Repeat_Seq
+            | N_Goto_Repeat_Seq =>
+            Res := Get_Sequence (Prop);
+            if Res /= Null_PSL_Node then
+               Res := Sem_Sequence (Get_Sequence (Prop));
+               Set_Sequence (Prop, Res);
+            end if;
+            return Prop;
          when N_Always
             | N_Never =>
             --  By extension, clock_event is allowed within outermost