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-rw-r--r--src/vhdl/translate/trans-chap12.adb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 1659d54fb..00e071010 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -16,7 +16,7 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
-with Configuration;
+with Vhdl.Configuration;
with Errorout; use Errorout;
with Std_Package; use Std_Package;
with Iirs_Utils; use Iirs_Utils;
@@ -419,7 +419,7 @@ package body Trans.Chap12 is
-- Write to file FILELIST all the files that are needed to link the design.
procedure Gen_Stubs
is
- use Configuration;
+ use Vhdl.Configuration;
-- Add all dependences of UNIT.
-- UNIT is not used, but added during link.
@@ -527,7 +527,7 @@ package body Trans.Chap12 is
procedure Elaborate (Config : Iir_Design_Unit; Whole : Boolean)
is
- use Configuration;
+ use Vhdl.Configuration;
Unit : Iir_Design_Unit;
Lib_Unit : Iir;