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-rw-r--r--src/vhdl/simulate/simul-simulation-main.adb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index fcac44e3d..956d0f3dc 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -1212,7 +1212,7 @@ package body Simul.Simulation.Main is
procedure Simulation_Entity (Top_Conf : Iir_Design_Unit)
is
use Grt.Errors;
- Stop : Boolean;
+ Ok : C_Boolean;
Status : Integer;
begin
Break_Time := Std_Time'Last;
@@ -1225,8 +1225,8 @@ package body Simul.Simulation.Main is
Debug (Reason_Start);
end if;
- Grt.Main.Run_Elab (Stop);
- if Stop then
+ Ok := Grt.Main.Run_Elab;
+ if not Ok then
return;
end if;