diff options
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-context.adb | 6 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 26 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 22 | ||||
| -rw-r--r-- | src/synth/synth-types.adb | 6 |
4 files changed, 30 insertions, 30 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb index 607c94555..95eb09baa 100644 --- a/src/synth/synth-context.adb +++ b/src/synth/synth-context.adb @@ -26,7 +26,7 @@ with Errorout; use Errorout; with Iirs_Utils; with Vhdl.Std_Package; -with Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; with Simul.Annotations; use Simul.Annotations; with Simul.Execution; @@ -90,8 +90,8 @@ package body Synth.Context is end if; when Iir_Kind_Array_Type_Definition => -- Well known array types. - if Btype = Ieee.Std_Logic_1164.Std_Logic_Vector_Type - or else Btype = Ieee.Std_Logic_1164.Std_Ulogic_Vector_Type + if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type + or else Btype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Vector_Type then return Alloc_Wire (Kind, Obj, Bounds_To_Range (Val.Bounds.D (1))); diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index cbc9f87d2..7a682dbff 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -21,7 +21,7 @@ with Ada.Unchecked_Conversion; with Ada.Unchecked_Deallocation; with Std_Names; -with Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; with Vhdl.Std_Package; with Errorout; use Errorout; with Simul.Execution; @@ -85,21 +85,21 @@ package body Synth.Expr is when Iir_Value_E8 => -- Std_logic. case Lit.E8 is - when Ieee.Std_Logic_1164.Std_Logic_0_Pos - | Ieee.Std_Logic_1164.Std_Logic_L_Pos => + when Vhdl.Ieee.Std_Logic_1164.Std_Logic_0_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_L_Pos => Val := 0; Zx := 0; - when Ieee.Std_Logic_1164.Std_Logic_1_Pos - | Ieee.Std_Logic_1164.Std_Logic_H_Pos => + when Vhdl.Ieee.Std_Logic_1164.Std_Logic_1_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_H_Pos => Val := 1; Zx := 0; - when Ieee.Std_Logic_1164.Std_Logic_U_Pos - | Ieee.Std_Logic_1164.Std_Logic_X_Pos - | Ieee.Std_Logic_1164.Std_Logic_D_Pos => + when Vhdl.Ieee.Std_Logic_1164.Std_Logic_U_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_X_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_D_Pos => Val := 1; Zx := 1; - when Ieee.Std_Logic_1164.Std_Logic_Z_Pos - | Ieee.Std_Logic_1164.Std_Logic_W_Pos => + when Vhdl.Ieee.Std_Logic_1164.Std_Logic_Z_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_W_Pos => Val := 0; Zx := 1; when others => @@ -696,11 +696,11 @@ package body Synth.Expr is end if; Lit := Get_Named_Entity (Right); if Lit = Vhdl.Std_Package.Bit_0 - or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_0 + or else Lit = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_0 then Posedge := False; elsif Lit = Vhdl.Std_Package.Bit_1 - or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_1 + or else Lit = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_1 then Posedge := True; else @@ -851,7 +851,7 @@ package body Synth.Expr is Imp : constant Iir := Get_Implementation (Expr); Clk : Net; begin - if Imp = Ieee.Std_Logic_1164.Rising_Edge then + if Imp = Vhdl.Ieee.Std_Logic_1164.Rising_Edge then Clk := Get_Net (Synth_Assoc_In (Syn_Inst, Get_Parameter_Association_Chain (Expr))); diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 3889cde3c..6acf95fac 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -27,7 +27,7 @@ with Errorout; use Errorout; with Vhdl.Sem_Expr; with Iirs_Utils; use Iirs_Utils; -with Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; with Evaluation; with Synth.Types; use Synth.Types; @@ -195,7 +195,7 @@ package body Synth.Stmts is El_Type : constant Iir := Get_Base_Type (Get_Element_Subtype (Get_Type (Expr))); begin - if El_Type = Ieee.Std_Logic_1164.Std_Ulogic_Type then + if El_Type = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type then declare use Evaluation.String_Utils; @@ -210,17 +210,17 @@ package body Synth.Stmts is Val := Shift_Left (Val, 1); Dc := Shift_Left (Dc, 1); case Get_Pos (Info, I) is - when Ieee.Std_Logic_1164.Std_Logic_0_Pos => + when Vhdl.Ieee.Std_Logic_1164.Std_Logic_0_Pos => Val := Val or 0; - when Ieee.Std_Logic_1164.Std_Logic_1_Pos => + when Vhdl.Ieee.Std_Logic_1164.Std_Logic_1_Pos => Val := Val or 1; - when Ieee.Std_Logic_1164.Std_Logic_U_Pos - | Ieee.Std_Logic_1164.Std_Logic_X_Pos - | Ieee.Std_Logic_1164.Std_Logic_Z_Pos - | Ieee.Std_Logic_1164.Std_Logic_W_Pos - | Ieee.Std_Logic_1164.Std_Logic_D_Pos - | Ieee.Std_Logic_1164.Std_Logic_L_Pos - | Ieee.Std_Logic_1164.Std_Logic_H_Pos => + when Vhdl.Ieee.Std_Logic_1164.Std_Logic_U_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_X_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_Z_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_W_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_D_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_L_Pos + | Vhdl.Ieee.Std_Logic_1164.Std_Logic_H_Pos => Dc := Dc or 1; when others => raise Internal_Error; diff --git a/src/synth/synth-types.adb b/src/synth/synth-types.adb index 88542ab6b..f1478fb18 100644 --- a/src/synth/synth-types.adb +++ b/src/synth/synth-types.adb @@ -20,7 +20,7 @@ with Types; use Types; with Vhdl.Std_Package; -with Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; with Iirs_Utils; use Iirs_Utils; with Simul.Environments; use Simul.Environments; @@ -30,8 +30,8 @@ with Errorout; use Errorout; package body Synth.Types is function Is_Bit_Type (Atype : Iir) return Boolean is begin - return Atype = Ieee.Std_Logic_1164.Std_Ulogic_Type - or else Atype = Ieee.Std_Logic_1164.Std_Logic_Type + return Atype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type + or else Atype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Type or else Atype = Vhdl.Std_Package.Boolean_Type_Definition or else Atype = Vhdl.Std_Package.Bit_Type_Definition; end Is_Bit_Type; |