1 files changed, 7 insertions, 0 deletions
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb
index e83cdb4ea..40c9e5d30 100644
--- a/src/synth/synthesis.adb
+++ b/src/synth/synthesis.adb
@@ -25,6 +25,7 @@ with Netlists.Expands;
 
 with Elab.Vhdl_Values.Debug;
 pragma Unreferenced (Elab.Vhdl_Values.Debug);
+with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
 
 with Synth.Vhdl_Insts; use Synth.Vhdl_Insts;
 
@@ -58,6 +59,8 @@ package body Synthesis is
          Synth_Initialize_Foreign.all;
       end if;
 
+      pragma Assert (Is_Expr_Pool_Empty);
+
       Unit := Get_Library_Unit (Design);
       if Get_Kind (Unit) = Iir_Kind_Foreign_Module then
          if Synth_Top_Foreign = null then
@@ -68,8 +71,12 @@ package body Synthesis is
          Synth_Top_Entity (Base, Design, Encoding, Inst);
       end if;
 
+      pragma Assert (Is_Expr_Pool_Empty);
+
       Synth.Vhdl_Insts.Synth_All_Instances;
 
+      pragma Assert (Is_Expr_Pool_Empty);
+
       if Errorout.Nbr_Errors > 0 then
          return No_Module;
       end if;