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-rw-r--r--src/simul/simul-vhdl_simul.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index f7a51b822..e5ca86a53 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2581,8 +2581,8 @@ package body Simul.Vhdl_Simul is
Grt.Errors.Fatal_Error;
end if;
- pragma Assert (Dst_Val.Typ.Wkind = Wkind_Sim);
Convert_Type_Width (Dst_Val.Typ);
+ pragma Assert (Dst_Val.Typ.Wkind = Wkind_Sim);
Dst := Synth.Vhdl_Expr.Get_Value_Memtyp (Dst_Val);
case Conv.Mode is