diff options
Diffstat (limited to 'pyGHDL/dom')
| -rw-r--r-- | pyGHDL/dom/Concurrent.py | 140 | ||||
| -rw-r--r-- | pyGHDL/dom/DesignUnit.py | 28 | ||||
| -rw-r--r-- | pyGHDL/dom/Expression.py | 128 | ||||
| -rw-r--r-- | pyGHDL/dom/InterfaceItem.py | 48 | ||||
| -rw-r--r-- | pyGHDL/dom/Literal.py | 4 | ||||
| -rw-r--r-- | pyGHDL/dom/NonStandard.py | 12 | ||||
| -rw-r--r-- | pyGHDL/dom/Object.py | 4 | ||||
| -rw-r--r-- | pyGHDL/dom/Sequential.py | 74 | ||||
| -rw-r--r-- | pyGHDL/dom/Subprogram.py | 16 | ||||
| -rw-r--r-- | pyGHDL/dom/Symbol.py | 20 | ||||
| -rw-r--r-- | pyGHDL/dom/Type.py | 44 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 50 | ||||
| -rw-r--r-- | pyGHDL/dom/_Utils.py | 8 | ||||
| -rw-r--r-- | pyGHDL/dom/__init__.py | 8 | ||||
| -rw-r--r-- | pyGHDL/dom/formatting/prettyprint.py | 198 |
15 files changed, 183 insertions, 599 deletions
diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index e7162cc81..560acafb2 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -74,27 +74,21 @@ from pyGHDL.dom._Utils import GetNameOfNode @export class GenericAssociationItem(VHDLModel_GenericAssociationItem, DOMMixin): - def __init__( - self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None - ): + def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None): super().__init__(actual, formal) DOMMixin.__init__(self, associationNode) @export class PortAssociationItem(VHDLModel_PortAssociationItem, DOMMixin): - def __init__( - self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None - ): + def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None): super().__init__(actual, formal) DOMMixin.__init__(self, associationNode) @export class ParameterAssociationItem(VHDLModel_ParameterAssociationItem, DOMMixin): - def __init__( - self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None - ): + def __init__(self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None): super().__init__(actual, formal) DOMMixin.__init__(self, associationNode) @@ -113,9 +107,7 @@ class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): DOMMixin.__init__(self, instantiationNode) @classmethod - def parse( - cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str - ) -> "ComponentInstantiation": + def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation": from pyGHDL.dom._Translate import ( GetNameFromNode, GetGenericMapAspect, @@ -123,12 +115,8 @@ class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): ) componentName = GetNameFromNode(instantiatedUnit) - genericAssociations = GetGenericMapAspect( - nodes.Get_Generic_Map_Aspect_Chain(instantiationNode) - ) - portAssociations = GetPortMapAspect( - nodes.Get_Port_Map_Aspect_Chain(instantiationNode) - ) + genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) + portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) return cls( instantiationNode, @@ -150,15 +138,11 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): genericAssociations: Iterable[AssociationItem] = None, portAssociations: Iterable[AssociationItem] = None, ): - super().__init__( - label, entityName, architectureName, genericAssociations, portAssociations - ) + super().__init__(label, entityName, architectureName, genericAssociations, portAssociations) DOMMixin.__init__(self, instantiationNode) @classmethod - def parse( - cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str - ) -> "EntityInstantiation": + def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": from pyGHDL.dom._Translate import ( GetNameFromNode, GetGenericMapAspect, @@ -173,12 +157,8 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): if architectureId != nodes.Null_Iir: architectureName = GetNameOfNode(architectureId) - genericAssociations = GetGenericMapAspect( - nodes.Get_Generic_Map_Aspect_Chain(instantiationNode) - ) - portAssociations = GetPortMapAspect( - nodes.Get_Port_Map_Aspect_Chain(instantiationNode) - ) + genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) + portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) return cls( instantiationNode, @@ -200,15 +180,11 @@ class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin) genericAssociations: Iterable[AssociationItem] = None, portAssociations: Iterable[AssociationItem] = None, ): - super().__init__( - label, configurationName, genericAssociations, portAssociations - ) + super().__init__(label, configurationName, genericAssociations, portAssociations) DOMMixin.__init__(self, instantiationNode) @classmethod - def parse( - cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str - ) -> "ConfigurationInstantiation": + def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation": from pyGHDL.dom._Translate import ( GetNameFromNode, GetGenericMapAspect, @@ -218,12 +194,8 @@ class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin) configurationId = nodes.Get_Configuration_Name(instantiatedUnit) configurationName = GetNameFromNode(configurationId) - genericAssociations = GetGenericMapAspect( - nodes.Get_Generic_Map_Aspect_Chain(instantiationNode) - ) - portAssociations = GetPortMapAspect( - nodes.Get_Port_Map_Aspect_Chain(instantiationNode) - ) + genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) + portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) return cls( instantiationNode, @@ -256,9 +228,7 @@ class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): # genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) # portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) - declaredItems = GetDeclaredItemsFromChainedNodes( - nodes.Get_Declaration_Chain(blockNode), "block", label - ) + declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(blockNode), "block", label) statements = GetConcurrentStatementsFromChainedNodes( nodes.Get_Concurrent_Statement_Chain(blockNode), "block", label ) @@ -280,9 +250,7 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): DOMMixin.__init__(self, processNode) @classmethod - def parse( - cls, processNode: Iir, label: str, hasSensitivityList: bool - ) -> "ProcessStatement": + def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes, @@ -295,9 +263,7 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): # sensitivityListNode = nodes.Get_Sensitivity_List(processNode) # print("sensi", GetIirKindOfNode(sensitivityListNode)) - declaredItems = GetDeclaredItemsFromChainedNodes( - nodes.Get_Declaration_Chain(processNode), "process", label - ) + declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label) statements = GetSequentialStatementsFromChainedNodes( nodes.Get_Sequential_Statement_Chain(processNode), "process", label ) @@ -334,14 +300,10 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch): alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) - declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "if-generate branch", alternativeLabel - ) + declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "if-generate branch", alternativeLabel) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetConcurrentStatementsFromChainedNodes( - statementChain, "if-generate branch", alternativeLabel - ) + statements = GetConcurrentStatementsFromChainedNodes(statementChain, "if-generate branch", alternativeLabel) return cls(generateNode, condition, declaredItems, statements, alternativeLabel) @@ -375,14 +337,10 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch): alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) - declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "elsif-generate branch", alternativeLabel - ) + declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "elsif-generate branch", alternativeLabel) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetConcurrentStatementsFromChainedNodes( - statementChain, "elsif-generate branch", alternativeLabel - ) + statements = GetConcurrentStatementsFromChainedNodes(statementChain, "elsif-generate branch", alternativeLabel) return cls(generateNode, condition, declaredItems, statements, alternativeLabel) @@ -413,14 +371,10 @@ class ElseGenerateBranch(VHDLModel_ElseGenerateBranch): alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) - declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "else-generate branch", alternativeLabel - ) + declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "else-generate branch", alternativeLabel) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetConcurrentStatementsFromChainedNodes( - statementChain, "else-generate branch", alternativeLabel - ) + statements = GetConcurrentStatementsFromChainedNodes(statementChain, "else-generate branch", alternativeLabel) return cls(generateNode, declaredItems, statements, alternativeLabel) @@ -488,9 +442,7 @@ class GenerateCase(VHDLModel_GenerateCase, DOMMixin): DOMMixin.__init__(self, node) @classmethod - def parse( - cls, caseNode: Iir, choices: Iterable[ConcurrentChoice] - ) -> "GenerateCase": + def parse(cls, caseNode: Iir, choices: Iterable[ConcurrentChoice]) -> "GenerateCase": from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, @@ -503,14 +455,10 @@ class GenerateCase(VHDLModel_GenerateCase, DOMMixin): alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) - declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "generate case", alternativeLabel - ) + declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "generate case", alternativeLabel) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetConcurrentStatementsFromChainedNodes( - statementChain, "generate case", alternativeLabel - ) + statements = GetConcurrentStatementsFromChainedNodes(statementChain, "generate case", alternativeLabel) return cls(caseNode, choices, declaredItems, statements, alternativeLabel) @@ -541,14 +489,10 @@ class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin): alternativeLabel = "" declarationChain = nodes.Get_Declaration_Chain(body) - declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "case-generate others", alternativeLabel - ) + declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "case-generate others", alternativeLabel) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetConcurrentStatementsFromChainedNodes( - statementChain, "case-generate others", alternativeLabel - ) + statements = GetConcurrentStatementsFromChainedNodes(statementChain, "case-generate others", alternativeLabel) return cls(caseNode, declaredItems, statements, alternativeLabel) @@ -589,9 +533,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): nodes.Iir_Kind.Choice_By_Name, nodes.Iir_Kind.Choice_By_Expression, ): - choiceExpression = GetExpressionFromNode( - nodes.Get_Choice_Expression(alternative) - ) + choiceExpression = GetExpressionFromNode(nodes.Get_Choice_Expression(alternative)) choice = IndexedGenerateChoice(alternative, choiceExpression) if sameAlternative: @@ -699,23 +641,17 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): body = nodes.Get_Generate_Statement_Body(generateNode) declarationChain = nodes.Get_Declaration_Chain(body) - declaredItems = GetDeclaredItemsFromChainedNodes( - declarationChain, "for-generate", label - ) + declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "for-generate", label) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetConcurrentStatementsFromChainedNodes( - statementChain, "for-generate", label - ) + statements = GetConcurrentStatementsFromChainedNodes(statementChain, "for-generate", label) return cls(generateNode, label, loopIndex, rng, declaredItems, statements) @export class WaveformElement(VHDLModel_WaveformElement, DOMMixin): - def __init__( - self, waveNode: Iir, expression: ExpressionUnion, after: ExpressionUnion - ): + def __init__(self, waveNode: Iir, expression: ExpressionUnion, after: ExpressionUnion): super().__init__(expression, after) DOMMixin.__init__(self, waveNode) @@ -735,9 +671,7 @@ class WaveformElement(VHDLModel_WaveformElement, DOMMixin): @export -class ConcurrentSimpleSignalAssignment( - VHDLModel_ConcurrentSimpleSignalAssignment, DOMMixin -): +class ConcurrentSimpleSignalAssignment(VHDLModel_ConcurrentSimpleSignalAssignment, DOMMixin): def __init__( self, assignmentNode: Iir, @@ -749,9 +683,7 @@ class ConcurrentSimpleSignalAssignment( DOMMixin.__init__(self, assignmentNode) @classmethod - def parse( - cls, assignmentNode: Iir, label: str - ) -> "ConcurrentSimpleSignalAssignment": + def parse(cls, assignmentNode: Iir, label: str) -> "ConcurrentSimpleSignalAssignment": from pyGHDL.dom._Translate import GetNameFromNode target = nodes.Get_Target(assignmentNode) @@ -784,8 +716,6 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): prefix = nodes.Get_Prefix(callNode) procedureName = GetNameFromNode(prefix) - parameterAssociations = GetParameterMapAspect( - nodes.Get_Parameter_Association_Chain(callNode) - ) + parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) return cls(concurrentCallNode, label, procedureName, parameterAssociations) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 3fe8f74bf..ae53a3476 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -133,9 +133,7 @@ class Entity(VHDLModel_Entity, DOMMixin): declaredItems: Iterable = None, statements: Iterable["ConcurrentStatement"] = None, ): - super().__init__( - identifier, contextItems, genericItems, portItems, declaredItems, statements - ) + super().__init__(identifier, contextItems, genericItems, portItems, declaredItems, statements) DOMMixin.__init__(self, node) @classmethod @@ -143,18 +141,14 @@ class Entity(VHDLModel_Entity, DOMMixin): name = GetNameOfNode(entityNode) generics = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(entityNode)) ports = GetPortsFromChainedNodes(nodes.Get_Port_Chain(entityNode)) - declaredItems = GetDeclaredItemsFromChainedNodes( - nodes.Get_Declaration_Chain(entityNode), "entity", name - ) + declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(entityNode), "entity", name) statements = GetConcurrentStatementsFromChainedNodes( nodes.Get_Concurrent_Statement_Chain(entityNode), "entity", name ) # FIXME: read use clauses - return cls( - entityNode, name, contextItems, generics, ports, declaredItems, statements - ) + return cls(entityNode, name, contextItems, generics, ports, declaredItems, statements) @export @@ -186,9 +180,7 @@ class Architecture(VHDLModel_Architecture, DOMMixin): # FIXME: read use clauses - return cls( - architectureNode, name, entity, contextItems, declaredItems, statements - ) + return cls(architectureNode, name, entity, contextItems, declaredItems, statements) @export @@ -231,15 +223,11 @@ class Package(VHDLModel_Package, DOMMixin): packageHeader = nodes.Get_Package_Header(packageNode) if packageHeader is not nodes.Null_Iir: - generics = GetGenericsFromChainedNodes( - nodes.Get_Generic_Chain(packageHeader) - ) + generics = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(packageHeader)) else: generics = [] - declaredItems = GetDeclaredItemsFromChainedNodes( - nodes.Get_Declaration_Chain(packageNode), "package", name - ) + declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(packageNode), "package", name) # FIXME: read use clauses @@ -261,9 +249,7 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin): @classmethod def parse(cls, packageBodyNode: Iir, contextItems: Iterable[ContextUnion]): name = GetNameOfNode(packageBodyNode) - declaredItems = GetDeclaredItemsFromChainedNodes( - nodes.Get_Declaration_Chain(packageBodyNode), "package", name - ) + declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(packageBodyNode), "package", name) # FIXME: read use clauses diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index ce5945d46..f3c7f56c6 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -127,45 +127,35 @@ class _ParseBinaryExpressionMixin: @export -class InverseExpression( - VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin -): +class InverseExpression(VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @export -class IdentityExpression( - VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin -): +class IdentityExpression(VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @export -class NegationExpression( - VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin -): +class NegationExpression(VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @export -class AbsoluteExpression( - VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin -): +class AbsoluteExpression(VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @export -class ParenthesisExpression( - VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpressionMixin -): +class ParenthesisExpression(VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpressionMixin): def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @@ -194,9 +184,7 @@ class FunctionCall(VHDLModel_FunctionCall, DOMMixin): class RangeExpression(VHDLModel_RangeExpression, DOMMixin): @classmethod - def parse( - cls, node: Iir - ) -> Union["AscendingRangeExpression", "DescendingRangeExpression"]: + def parse(cls, node: Iir) -> Union["AscendingRangeExpression", "DescendingRangeExpression"]: from pyGHDL.dom._Translate import GetExpressionFromNode direction = nodes.Get_Direction(node) @@ -224,72 +212,56 @@ class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin): @export -class AdditionExpression( - VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class AdditionExpression(VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class SubtractionExpression( - VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class SubtractionExpression(VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class ConcatenationExpression( - VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class ConcatenationExpression(VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class MultiplyExpression( - VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class MultiplyExpression(VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class DivisionExpression( - VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class DivisionExpression(VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class RemainderExpression( - VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class RemainderExpression(VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class ModuloExpression( - VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class ModuloExpression(VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class ExponentiationExpression( - VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class ExponentiationExpression(VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -345,153 +317,119 @@ class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressio @export -class UnequalExpression( - VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class UnequalExpression(VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class LessThanExpression( - VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class LessThanExpression(VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class LessEqualExpression( - VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class LessEqualExpression(VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class GreaterThanExpression( - VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class GreaterThanExpression(VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class GreaterEqualExpression( - VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class GreaterEqualExpression(VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class MatchingEqualExpression( - VHDLModel_MatchingEqualExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class MatchingEqualExpression(VHDLModel_MatchingEqualExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class MatchingUnequalExpression( - VHDLModel_MatchingUnequalExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class MatchingUnequalExpression(VHDLModel_MatchingUnequalExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class MatchingLessThanExpression( - VHDLModel_MatchingLessThanExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class MatchingLessThanExpression(VHDLModel_MatchingLessThanExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class MatchingLessEqualExpression( - VHDLModel_MatchingLessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class MatchingLessEqualExpression(VHDLModel_MatchingLessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class MatchingGreaterThanExpression( - VHDLModel_MatchingGreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class MatchingGreaterThanExpression(VHDLModel_MatchingGreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class MatchingGreaterEqualExpression( - VHDLModel_MatchingGreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class MatchingGreaterEqualExpression(VHDLModel_MatchingGreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class ShiftRightLogicExpression( - VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class ShiftLeftLogicExpression( - VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class ShiftRightArithmeticExpression( - VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class ShiftLeftArithmeticExpression( - VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class RotateRightExpression( - VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class RotateRightExpression(VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export -class RotateLeftExpression( - VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpressionMixin -): +class RotateLeftExpression(VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpressionMixin): def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -596,9 +534,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): choices.append(OthersAggregateElement(item, value)) else: raise DOMException( - "Unknown choice kind '{kind}' in aggregate '{aggr}'.".format( - kind=kind.name, aggr=node - ) + "Unknown choice kind '{kind}' in aggregate '{aggr}'.".format(kind=kind.name, aggr=node) ) return cls(node, choices) diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index af1b681cd..4bc65cf95 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -180,11 +180,7 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin): subtypeIndication = GetSubtypeIndicationFromNode(portNode, "port", name) defaultValue = nodes.Get_Default_Value(portNode) - value = ( - GetExpressionFromNode(defaultValue) - if defaultValue != nodes.Null_Iir - else None - ) + value = GetExpressionFromNode(defaultValue) if defaultValue != nodes.Null_Iir else None return cls( portNode, @@ -198,9 +194,7 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin): @export -class ParameterConstantInterfaceItem( - VHDLModel_ParameterConstantInterfaceItem, DOMMixin -): +class ParameterConstantInterfaceItem(VHDLModel_ParameterConstantInterfaceItem, DOMMixin): def __init__( self, node: Iir, @@ -216,16 +210,10 @@ class ParameterConstantInterfaceItem( def parse(cls, parameterNode: Iir) -> "ParameterConstantInterfaceItem": name = GetNameOfNode(parameterNode) mode = GetModeOfNode(parameterNode) - subtypeIndication = GetSubtypeIndicationFromNode( - parameterNode, "parameter", name - ) + subtypeIndication = GetSubtypeIndicationFromNode(parameterNode, "parameter", name) defaultValue = nodes.Get_Default_Value(parameterNode) - value = ( - GetExpressionFromNode(defaultValue) - if defaultValue != nodes.Null_Iir - else None - ) + value = GetExpressionFromNode(defaultValue) if defaultValue != nodes.Null_Iir else None return cls( parameterNode, @@ -239,9 +227,7 @@ class ParameterConstantInterfaceItem( @export -class ParameterVariableInterfaceItem( - VHDLModel_ParameterVariableInterfaceItem, DOMMixin -): +class ParameterVariableInterfaceItem(VHDLModel_ParameterVariableInterfaceItem, DOMMixin): def __init__( self, node: Iir, @@ -257,16 +243,10 @@ class ParameterVariableInterfaceItem( def parse(cls, parameterNode: Iir) -> "ParameterVariableInterfaceItem": name = GetNameOfNode(parameterNode) mode = GetModeOfNode(parameterNode) - subtypeIndication = GetSubtypeIndicationFromNode( - parameterNode, "parameter", name - ) + subtypeIndication = GetSubtypeIndicationFromNode(parameterNode, "parameter", name) defaultValue = nodes.Get_Default_Value(parameterNode) - value = ( - GetExpressionFromNode(defaultValue) - if defaultValue != nodes.Null_Iir - else None - ) + value = GetExpressionFromNode(defaultValue) if defaultValue != nodes.Null_Iir else None return cls( parameterNode, @@ -296,16 +276,10 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi def parse(cls, parameterNode: Iir) -> "ParameterSignalInterfaceItem": name = GetNameOfNode(parameterNode) mode = GetModeOfNode(parameterNode) - subtypeIndication = GetSubtypeIndicationFromNode( - parameterNode, "parameter", name - ) + subtypeIndication = GetSubtypeIndicationFromNode(parameterNode, "parameter", name) defaultValue = nodes.Get_Default_Value(parameterNode) - value = ( - GetExpressionFromNode(defaultValue) - if defaultValue != nodes.Null_Iir - else None - ) + value = GetExpressionFromNode(defaultValue) if defaultValue != nodes.Null_Iir else None return cls( parameterNode, @@ -332,9 +306,7 @@ class ParameterFileInterfaceItem(VHDLModel_ParameterFileInterfaceItem, DOMMixin) @classmethod def parse(cls, parameterNode: Iir) -> "ParameterFileInterfaceItem": name = GetNameOfNode(parameterNode) - subtypeIndication = GetSubtypeIndicationFromNode( - parameterNode, "parameter", name - ) + subtypeIndication = GetSubtypeIndicationFromNode(parameterNode, "parameter", name) return cls( parameterNode, diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index 26be52ec8..54bcc2fc2 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -150,9 +150,7 @@ class StringLiteral(VHDLModel_StringLiteral, DOMMixin): @classmethod def parse(cls, literalNode: Iir) -> "StringLiteral": if nodes.Get_Bit_String_Base(literalNode) is nodes.NumberBaseType.Base_None: - value = str_table.Get_String8_Ptr( - nodes.Get_String8_Id(literalNode), nodes.Get_String_Length(literalNode) - ) + value = str_table.Get_String8_Ptr(nodes.Get_String8_Id(literalNode), nodes.Get_String_Length(literalNode)) return cls(literalNode, value) else: print("[NOT IMPLEMENTED] Bit String Literal not supported yet") diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index 1cd98b4fa..b0242e260 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -159,12 +159,8 @@ class Document(VHDLModel_Document): bufferLength = sourceLength + 128 self.__ghdlFileID = name_table.Get_Identifier(str(self._filename)) dirId = name_table.Null_Identifier - self.__ghdlSourceFileEntry = files_map.Reserve_Source_File( - dirId, self.__ghdlFileID, bufferLength - ) - files_map_editor.Fill_Text( - self.__ghdlSourceFileEntry, ctypes.c_char_p(sourcesBytes), sourceLength - ) + self.__ghdlSourceFileEntry = files_map.Reserve_Source_File(dirId, self.__ghdlFileID, bufferLength) + files_map_editor.Fill_Text(self.__ghdlSourceFileEntry, ctypes.c_char_p(sourcesBytes), sourceLength) CheckForErrors() @@ -241,9 +237,7 @@ class Document(VHDLModel_Document): self.VerificationModes.append(vmod) else: - raise DOMException( - "Unknown design unit kind '{kind}'.".format(kind=nodeKind.name) - ) + raise DOMException("Unknown design unit kind '{kind}'.".format(kind=nodeKind.name)) @property def LibGHDLProcessingTime(self) -> float: diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py index def09d50c..351bcddf0 100644 --- a/pyGHDL/dom/Object.py +++ b/pyGHDL/dom/Object.py @@ -107,9 +107,7 @@ class DeferredConstant(VHDLModel_DeferredConstant, DOMMixin): from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode name = GetNameOfNode(constantNode) - subtypeIndication = GetSubtypeIndicationFromNode( - constantNode, "deferred constant", name - ) + subtypeIndication = GetSubtypeIndicationFromNode(constantNode, "deferred constant", name) return cls( constantNode, diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index be4793b2a..9e1af5b32 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -89,9 +89,7 @@ class IfBranch(VHDLModel_IfBranch): condition = GetExpressionFromNode(nodes.Get_Condition(branchNode)) statementChain = nodes.Get_Sequential_Statement_Chain(branchNode) - statements = GetSequentialStatementsFromChainedNodes( - statementChain, "if branch", label - ) + statements = GetSequentialStatementsFromChainedNodes(statementChain, "if branch", label) return cls(branchNode, condition, statements) @@ -116,9 +114,7 @@ class ElsifBranch(VHDLModel_ElsifBranch): condition = GetExpressionFromNode(condition) statementChain = nodes.Get_Sequential_Statement_Chain(branchNode) - statements = GetSequentialStatementsFromChainedNodes( - statementChain, "elsif branch", label - ) + statements = GetSequentialStatementsFromChainedNodes(statementChain, "elsif branch", label) return cls(branchNode, condition, statements) @@ -140,9 +136,7 @@ class ElseBranch(VHDLModel_ElseBranch): ) statementChain = nodes.Get_Sequential_Statement_Chain(branchNode) - statements = GetSequentialStatementsFromChainedNodes( - statementChain, "else branch", label - ) + statements = GetSequentialStatementsFromChainedNodes(statementChain, "else branch", label) return cls(branchNode, statements) @@ -208,15 +202,11 @@ class Case(VHDLModel_Case, DOMMixin): DOMMixin.__init__(self, node) @classmethod - def parse( - cls, caseNode: Iir, choices: Iterable[SequentialChoice], label: str - ) -> "Case": + def parse(cls, caseNode: Iir, choices: Iterable[SequentialChoice], label: str) -> "Case": from pyGHDL.dom._Translate import GetSequentialStatementsFromChainedNodes statementChain = nodes.Get_Associated_Chain(caseNode) - statements = GetSequentialStatementsFromChainedNodes( - statementChain, "case", label - ) + statements = GetSequentialStatementsFromChainedNodes(statementChain, "case", label) return cls(caseNode, choices, statements) @@ -240,9 +230,7 @@ class OthersCase(VHDLModel_OthersCase, DOMMixin): return cls(caseNode) statementChain = nodes.Get_Concurrent_Statement_Chain(body) - statements = GetSequentialStatementsFromChainedNodes( - statementChain, "case others", label - ) + statements = GetSequentialStatementsFromChainedNodes(statementChain, "case others", label) return cls(caseNode, statements) @@ -283,9 +271,7 @@ class CaseStatement(VHDLModel_CaseStatement, DOMMixin): nodes.Iir_Kind.Choice_By_Name, nodes.Iir_Kind.Choice_By_Expression, ): - choiceExpression = GetExpressionFromNode( - nodes.Get_Choice_Expression(alternative) - ) + choiceExpression = GetExpressionFromNode(nodes.Get_Choice_Expression(alternative)) choice = IndexedChoice(alternative, choiceExpression) if sameAlternative: @@ -390,17 +376,13 @@ class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin): ) statementChain = nodes.Get_Sequential_Statement_Chain(loopNode) - statements = GetSequentialStatementsFromChainedNodes( - statementChain, "for", label - ) + statements = GetSequentialStatementsFromChainedNodes(statementChain, "for", label) return cls(loopNode, loopIndex, rng, statements, label) @export -class SequentialSimpleSignalAssignment( - VHDLModel_SequentialSimpleSignalAssignment, DOMMixin -): +class SequentialSimpleSignalAssignment(VHDLModel_SequentialSimpleSignalAssignment, DOMMixin): def __init__( self, assignmentNode: Iir, @@ -412,9 +394,7 @@ class SequentialSimpleSignalAssignment( DOMMixin.__init__(self, assignmentNode) @classmethod - def parse( - cls, assignmentNode: Iir, label: str = None - ) -> "SequentialSimpleSignalAssignment": + def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialSimpleSignalAssignment": from pyGHDL.dom._Translate import GetNameFromNode target = nodes.Get_Target(assignmentNode) @@ -447,9 +427,7 @@ class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin): prefix = nodes.Get_Prefix(call) procedureName = GetNameFromNode(prefix) - parameterAssociations = GetParameterMapAspect( - nodes.Get_Parameter_Association_Chain(callNode) - ) + parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) return cls(callNode, procedureName, parameterAssociations, label) @@ -473,17 +451,9 @@ class SequentialAssertStatement(VHDLModel_SequentialAssertStatement, DOMMixin): condition = GetExpressionFromNode(nodes.Get_Assertion_Condition(assertNode)) messageNode = nodes.Get_Report_Expression(assertNode) - message = ( - None - if messageNode is nodes.Null_Iir - else GetExpressionFromNode(messageNode) - ) + message = None if messageNode is nodes.Null_Iir else GetExpressionFromNode(messageNode) severityNode = nodes.Get_Severity_Expression(assertNode) - severity = ( - None - if severityNode is nodes.Null_Iir - else GetExpressionFromNode(severityNode) - ) + severity = None if severityNode is nodes.Null_Iir else GetExpressionFromNode(severityNode) return cls(assertNode, condition, message, severity, label) @@ -506,11 +476,7 @@ class SequentialReportStatement(VHDLModel_SequentialReportStatement, DOMMixin): message = GetExpressionFromNode(nodes.Get_Report_Expression(reportNode)) severityNode = nodes.Get_Severity_Expression(reportNode) - severity = ( - None - if severityNode is nodes.Null_Iir - else GetExpressionFromNode(severityNode) - ) + severity = None if severityNode is nodes.Null_Iir else GetExpressionFromNode(severityNode) return cls(reportNode, message, severity, label) @@ -539,17 +505,9 @@ class WaitStatement(VHDLModel_WaitStatement, DOMMixin): print(GetIirKindOfNode(sensitivityListNode)) conditionNode = nodes.Get_Condition_Clause(waitNode) - condition = ( - None - if conditionNode is nodes.Null_Iir - else GetExpressionFromNode(conditionNode) - ) + condition = None if conditionNode is nodes.Null_Iir else GetExpressionFromNode(conditionNode) timeoutNode = nodes.Get_Timeout_Clause(waitNode) - timeout = ( - None - if timeoutNode is nodes.Null_Iir - else GetExpressionFromNode(timeoutNode) - ) + timeout = None if timeoutNode is nodes.Null_Iir else GetExpressionFromNode(timeoutNode) return cls(waitNode, sensitivityList, condition, timeout, label) diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py index 32635f693..ac8916792 100644 --- a/pyGHDL/dom/Subprogram.py +++ b/pyGHDL/dom/Subprogram.py @@ -63,9 +63,7 @@ class Function(VHDLModel_Function, DOMMixin): # TODO: move to model self._genericItems = [] if genericItems is None else [g for g in genericItems] - self._parameterItems = ( - [] if parameterItems is None else [p for p in parameterItems] - ) + self._parameterItems = [] if parameterItems is None else [p for p in parameterItems] self._returnType = returnType @classmethod @@ -78,9 +76,7 @@ class Function(VHDLModel_Function, DOMMixin): functionName = GetNameOfNode(functionNode) generics = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(functionNode)) - parameters = GetParameterFromChainedNodes( - nodes.Get_Interface_Declaration_Chain(functionNode) - ) + parameters = GetParameterFromChainedNodes(nodes.Get_Interface_Declaration_Chain(functionNode)) returnType = nodes.Get_Return_Type_Mark(functionNode) returnTypeName = GetNameOfNode(returnType) @@ -103,9 +99,7 @@ class Procedure(VHDLModel_Procedure, DOMMixin): # TODO: move to model self._genericItems = [] if genericItems is None else [g for g in genericItems] - self._parameterItems = ( - [] if parameterItems is None else [p for p in parameterItems] - ) + self._parameterItems = [] if parameterItems is None else [p for p in parameterItems] @classmethod def parse(cls, procedureNode: Iir) -> "Procedure": @@ -117,8 +111,6 @@ class Procedure(VHDLModel_Procedure, DOMMixin): procedureName = GetNameOfNode(procedureNode) generics = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(procedureNode)) - parameters = GetParameterFromChainedNodes( - nodes.Get_Interface_Declaration_Chain(procedureNode) - ) + parameters = GetParameterFromChainedNodes(nodes.Get_Interface_Declaration_Chain(procedureNode)) return cls(procedureNode, procedureName, generics, parameters) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index f52afbb18..d290b3d70 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -70,9 +70,7 @@ class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin): @export -class ConstrainedScalarSubtypeSymbol( - VHDLModel_ConstrainedScalarSubtypeSymbol, DOMMixin -): +class ConstrainedScalarSubtypeSymbol(VHDLModel_ConstrainedScalarSubtypeSymbol, DOMMixin): def __init__(self, node: Iir, subtypeName: Name, rng: Range = None): super().__init__(subtypeName, rng) DOMMixin.__init__(self, node) @@ -83,12 +81,8 @@ class ConstrainedScalarSubtypeSymbol( @export -class ConstrainedCompositeSubtypeSymbol( - VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin -): - def __init__( - self, node: Iir, subtypeName: Name, constraints: List[ConstraintUnion] = None - ): +class ConstrainedCompositeSubtypeSymbol(VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin): + def __init__(self, node: Iir, subtypeName: Name, constraints: List[ConstraintUnion] = None): super().__init__(subtypeName, constraints) DOMMixin.__init__(self, node) @@ -98,9 +92,7 @@ class ConstrainedCompositeSubtypeSymbol( @export -class SimpleObjectOrFunctionCallSymbol( - VHDLModel_SimpleObjectOrFunctionCallSymbol, DOMMixin -): +class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbol, DOMMixin): @classmethod def parse(cls, node: Iir): from pyGHDL.dom._Translate import GetNameFromNode @@ -110,9 +102,7 @@ class SimpleObjectOrFunctionCallSymbol( @export -class IndexedObjectOrFunctionCallSymbol( - VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin -): +class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin): def __init__(self, node: Iir, name: Name): super().__init__(name) DOMMixin.__init__(self, node) diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index deb315d9d..48cf50418 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -143,9 +143,7 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): if secondaryUnit == primaryUnit: continue - physicalLiteral = PhysicalIntegerLiteral.parse( - nodes.Get_Physical_Literal(secondaryUnit) - ) + physicalLiteral = PhysicalIntegerLiteral.parse(nodes.Get_Physical_Literal(secondaryUnit)) units.append((secondaryUnitName, physicalLiteral)) @@ -154,9 +152,7 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): @export class ArrayType(VHDLModel_ArrayType, DOMMixin): - def __init__( - self, node: Iir, identifier: str, indices: List, elementSubtype: SubtypeOrSymbol - ): + def __init__(self, node: Iir, identifier: str, indices: List, elementSubtype: SubtypeOrSymbol): super().__init__(identifier, indices, elementSubtype) DOMMixin.__init__(self, node) @@ -182,12 +178,8 @@ class ArrayType(VHDLModel_ArrayType, DOMMixin): ) ) - elementSubtypeIndication = nodes.Get_Element_Subtype_Indication( - typeDefinitionNode - ) - elementSubtype = GetSubtypeIndicationFromIndicationNode( - elementSubtypeIndication, "array declaration", typeName - ) + elementSubtypeIndication = nodes.Get_Element_Subtype_Indication(typeDefinitionNode) + elementSubtype = GetSubtypeIndicationFromIndicationNode(elementSubtypeIndication, "array declaration", typeName) return cls(typeDefinitionNode, typeName, indices, elementSubtype) @@ -204,9 +196,7 @@ class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin): from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode elementName = GetNameOfNode(elementDeclarationNode) - elementType = GetSubtypeIndicationFromNode( - elementDeclarationNode, "record element", elementName - ) + elementType = GetSubtypeIndicationFromNode(elementDeclarationNode, "record element", elementName) return cls( elementDeclarationNode, @@ -219,9 +209,7 @@ class RecordTypeElement(VHDLModel_RecordTypeElement, DOMMixin): @export class RecordType(VHDLModel_RecordType, DOMMixin): - def __init__( - self, node: Iir, identifier: str, elements: List[RecordTypeElement] = None - ): + def __init__(self, node: Iir, identifier: str, elements: List[RecordTypeElement] = None): super().__init__(identifier, elements) DOMMixin.__init__(self, node) @@ -264,9 +252,7 @@ class RecordType(VHDLModel_RecordType, DOMMixin): @export class ProtectedType(VHDLModel_ProtectedType, DOMMixin): - def __init__( - self, node: Iir, identifier: str, methods: Union[List, Iterator] = None - ): + def __init__(self, node: Iir, identifier: str, methods: Union[List, Iterator] = None): super().__init__(identifier, methods) DOMMixin.__init__(self, node) @@ -288,9 +274,7 @@ class ProtectedType(VHDLModel_ProtectedType, DOMMixin): @export class ProtectedTypeBody(VHDLModel_ProtectedTypeBody, DOMMixin): - def __init__( - self, node: Iir, identifier: str, declaredItems: Union[List, Iterator] = None - ): + def __init__(self, node: Iir, identifier: str, declaredItems: Union[List, Iterator] = None): super().__init__(identifier, declaredItems) DOMMixin.__init__(self, node) @@ -319,12 +303,8 @@ class AccessType(VHDLModel_AccessType, DOMMixin): def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "AccessType": from pyGHDL.dom._Translate import GetSubtypeIndicationFromIndicationNode - designatedSubtypeIndication = nodes.Get_Designated_Subtype_Indication( - typeDefinitionNode - ) - designatedSubtype = GetSubtypeIndicationFromIndicationNode( - designatedSubtypeIndication, "access type", typeName - ) + designatedSubtypeIndication = nodes.Get_Designated_Subtype_Indication(typeDefinitionNode) + designatedSubtype = GetSubtypeIndicationFromIndicationNode(designatedSubtypeIndication, "access type", typeName) return cls(typeDefinitionNode, typeName, designatedSubtype) @@ -341,9 +321,7 @@ class FileType(VHDLModel_FileType, DOMMixin): designatedSubtypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode) designatedSubtypeName = GetNameOfNode(designatedSubtypeMark) - designatedSubtype = SimpleSubtypeSymbol( - typeDefinitionNode, designatedSubtypeName - ) + designatedSubtype = SimpleSubtypeSymbol(typeDefinitionNode, designatedSubtypeName) return cls(typeDefinitionNode, typeName, designatedSubtype) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 43c443cc1..723b13f69 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -227,9 +227,7 @@ def GetArrayConstraintsFromSubtypeIndication( subtypeIndication: Iir, ) -> List[ConstraintUnion]: constraints = [] - for constraint in utils.flist_iter( - nodes.Get_Index_Constraint_List(subtypeIndication) - ): + for constraint in utils.flist_iter(nodes.Get_Index_Constraint_List(subtypeIndication)): constraintKind = GetIirKindOfNode(constraint) if constraintKind == nodes.Iir_Kind.Range_Expression: constraints.append(RangeExpression.parse(constraint)) @@ -332,9 +330,7 @@ def GetSubtypeIndicationFromNode(node: Iir, entity: str, name: str) -> SubtypeOr @export -def GetSubtypeIndicationFromIndicationNode( - subtypeIndicationNode: Iir, entity: str, name: str -) -> SubtypeOrSymbol: +def GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode: Iir, entity: str, name: str) -> SubtypeOrSymbol: if subtypeIndicationNode is nodes.Null_Iir: raise ValueError("Parameter 'subtypeIndicationNode' is 'Null_Iir'.") @@ -384,9 +380,7 @@ def GetCompositeConstrainedSubtypeFromNode( simpleTypeMark = SimpleName(typeMark, typeMarkName) constraints = GetArrayConstraintsFromSubtypeIndication(subtypeIndicationNode) - return ConstrainedCompositeSubtypeSymbol( - subtypeIndicationNode, simpleTypeMark, constraints - ) + return ConstrainedCompositeSubtypeSymbol(subtypeIndicationNode, simpleTypeMark, constraints) @export @@ -659,9 +653,7 @@ def GetParameterFromChainedNodes( yield param -def GetMapAspect( - mapAspect: Iir, cls: Type, entity: str -) -> Generator[AssociationItem, None, None]: +def GetMapAspect(mapAspect: Iir, cls: Type, entity: str) -> Generator[AssociationItem, None, None]: for generic in utils.chain_iter(mapAspect): kind = GetIirKindOfNode(generic) if kind is nodes.Iir_Kind.Association_Element_By_Expression: @@ -707,9 +699,7 @@ def GetParameterMapAspect( return GetMapAspect(parameterMapAspect, ParameterAssociationItem, "parameter") -def GetDeclaredItemsFromChainedNodes( - nodeChain: Iir, entity: str, name: str -) -> Generator[ModelEntity, None, None]: +def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str) -> Generator[ModelEntity, None, None]: item = nodeChain lastKind = None while item != nodes.Null_Iir: @@ -821,27 +811,15 @@ def GetDeclaredItemsFromChainedNodes( yield PackageInstantiation.parse(item) elif kind == nodes.Iir_Kind.Configuration_Specification: - print( - "[NOT IMPLEMENTED] Configuration specification in {name}".format( - name=name - ) - ) + print("[NOT IMPLEMENTED] Configuration specification in {name}".format(name=name)) elif kind == nodes.Iir_Kind.Psl_Default_Clock: yield DefaultClock.parse(item) elif kind == nodes.Iir_Kind.Group_Declaration: print("[NOT IMPLEMENTED] Group declaration in {name}".format(name=name)) elif kind == nodes.Iir_Kind.Group_Template_Declaration: - print( - "[NOT IMPLEMENTED] Group template declaration in {name}".format( - name=name - ) - ) + print("[NOT IMPLEMENTED] Group template declaration in {name}".format(name=name)) elif kind == nodes.Iir_Kind.Disconnection_Specification: - print( - "[NOT IMPLEMENTED] Disconnect specification in {name}".format( - name=name - ) - ) + print("[NOT IMPLEMENTED] Disconnect specification in {name}".format(name=name)) else: position = Position.parse(item) raise DOMException( @@ -920,9 +898,7 @@ def GetConcurrentStatementsFromChainedNodes( if instantiatedUnitKind == nodes.Iir_Kind.Entity_Aspect_Entity: yield EntityInstantiation.parse(statement, instantiatedUnit, label) elif instantiatedUnitKind == nodes.Iir_Kind.Entity_Aspect_Configuration: - yield ConfigurationInstantiation.parse( - statement, instantiatedUnit, label - ) + yield ConfigurationInstantiation.parse(statement, instantiatedUnit, label) elif instantiatedUnitKind == nodes.Iir_Kind.Simple_Name: yield ComponentInstantiation.parse(statement, instantiatedUnit, label) else: @@ -992,9 +968,7 @@ def GetSequentialStatementsFromChainedNodes( yield WaitStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Procedure_Call_Statement: print( - "[NOT IMPLEMENTED] Procedure call (label: '{label}') at line {line}".format( - label=label, line=pos.Line - ) + "[NOT IMPLEMENTED] Procedure call (label: '{label}') at line {line}".format(label=label, line=pos.Line) ) elif kind == nodes.Iir_Kind.Report_Statement: yield SequentialReportStatement.parse(statement, label) @@ -1002,9 +976,7 @@ def GetSequentialStatementsFromChainedNodes( yield SequentialAssertStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Null_Statement: print( - "[NOT IMPLEMENTED] null statement (label: '{label}') at line {line}".format( - label=label, line=pos.Line - ) + "[NOT IMPLEMENTED] null statement (label: '{label}') at line {line}".format(label=label, line=pos.Line) ) else: raise DOMException( diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index dbb39f43d..8fcfd7667 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -63,14 +63,10 @@ def CheckForErrors() -> None: message = errorout_memory.Get_Error_Message(i + 1) errors.append( - "{file}:{line}:{column}: {msg}".format( - file=fileName, line=rec.line, column=rec.offset, msg=message - ) + "{file}:{line}:{column}: {msg}".format(file=fileName, line=rec.line, column=rec.offset, msg=message) ) - raise DOMException("Error raised in libghdl.") from LibGHDLException( - "libghdl: Internal error.", errors - ) + raise DOMException("Error raised in libghdl.") from LibGHDLException("libghdl: Internal error.", errors) @export diff --git a/pyGHDL/dom/__init__.py b/pyGHDL/dom/__init__.py index 20c90a1d1..dc58c42d0 100644 --- a/pyGHDL/dom/__init__.py +++ b/pyGHDL/dom/__init__.py @@ -59,9 +59,7 @@ class Position: def parse(cls, node: Iir) -> "Position": """Return the source code position of a IIR node.""" if node == nodes.Null_Iir: - raise ValueError( - "Position.parse(): Parameter 'node' must not be 'Null_iir'." - ) + raise ValueError("Position.parse(): Parameter 'node' must not be 'Null_iir'.") location = nodes.Get_Location(node) file = files_map.Location_To_File(location) @@ -85,9 +83,7 @@ class Position: return self._column def __str__(self): - return "{file}:{line}:{column}".format( - file=self._filename, line=self._line, column=self._column - ) + return "{file}:{line}:{column}".format(file=self._filename, line=self._line, column=self._column) @export diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 6c0f06061..4a28b9905 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -119,18 +119,12 @@ class PrettyPrint: prefix = " " * level buffer.append("{prefix}Libraries:".format(prefix=prefix)) for library in design.Libraries.values(): - buffer.append( - "{prefix} - Name: {name}".format( - prefix=prefix, name=library.Identifier - ) - ) + buffer.append("{prefix} - Name: {name}".format(prefix=prefix, name=library.Identifier)) for line in self.formatLibrary(library, level + 2): buffer.append(line) buffer.append("{prefix}Documents:".format(prefix=prefix)) for document in design.Documents: - buffer.append( - "{prefix} - Path: '{doc!s}':".format(doc=document.Path, prefix=prefix) - ) + buffer.append("{prefix} - Path: '{doc!s}':".format(doc=document.Path, prefix=prefix)) for line in self.formatDocument(document, level + 2): buffer.append(line) @@ -145,17 +139,13 @@ class PrettyPrint: "{prefix} - {name}({architectures})".format( prefix=prefix, name=entity.Identifier, - architectures=", ".join( - [a.Identifier for a in entity.Architectures] - ), + architectures=", ".join([a.Identifier for a in entity.Architectures]), ) ) buffer.append("{prefix}Packages:".format(prefix=prefix)) for package in library.Packages: if isinstance(package, Package): - buffer.append( - "{prefix} - {name}".format(prefix=prefix, name=package.Identifier) - ) + buffer.append("{prefix} - {name}".format(prefix=prefix, name=package.Identifier)) elif isinstance(package, PackageInstantiation): buffer.append( "{prefix} - {name} instantiate from {package}".format( @@ -166,16 +156,10 @@ class PrettyPrint: ) buffer.append("{prefix}Configurations:".format(prefix=prefix)) for configuration in library.Configurations: - buffer.append( - "{prefix} - {name}".format( - prefix=prefix, name=configuration.Identifier - ) - ) + buffer.append("{prefix} - {name}".format(prefix=prefix, name=configuration.Identifier)) buffer.append("{prefix}Contexts:".format(prefix=prefix)) for context in library.Contexts: - buffer.append( - "{prefix} - {name}".format(prefix=prefix, name=context.Identifier) - ) + buffer.append("{prefix} - {name}".format(prefix=prefix, name=context.Identifier)) return buffer @@ -243,15 +227,11 @@ class PrettyPrint: buffer.append("{prefix} ...".format(prefix=prefix)) buffer.append("{prefix} Architecures:".format(prefix=prefix)) for item in entity.Architectures: - buffer.append( - "{prefix} - {name}".format(prefix=prefix, name=item.Identifier) - ) + buffer.append("{prefix} - {name}".format(prefix=prefix, name=item.Identifier)) return buffer - def formatArchitecture( - self, architecture: Architecture, level: int = 0 - ) -> StringBuffer: + def formatArchitecture(self, architecture: Architecture, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level buffer.append( @@ -263,11 +243,7 @@ class PrettyPrint: column=architecture.Position.Column, ) ) - buffer.append( - "{prefix} Entity: {entity}".format( - entity=architecture.Entity.SymbolName, prefix=prefix - ) - ) + buffer.append("{prefix} Entity: {entity}".format(entity=architecture.Entity.SymbolName, prefix=prefix)) buffer.append("{prefix} Declared:".format(prefix=prefix)) for item in architecture.DeclaredItems: for line in self.formatDeclaredItems(item, level + 2): @@ -287,11 +263,7 @@ class PrettyPrint: def formatComponent(self, component: Component, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append( - "{prefix}- Component: {name}".format( - name=component.Identifier, prefix=prefix - ) - ) + buffer.append("{prefix}- Component: {name}".format(name=component.Identifier, prefix=prefix)) buffer.append("{prefix} Generics:".format(prefix=prefix)) for generic in component.GenericItems: for line in self.formatGeneric(generic, level + 1): @@ -322,19 +294,11 @@ class PrettyPrint: return buffer - def formatPackageInstance( - self, package: PackageInstantiation, level: int = 0 - ) -> StringBuffer: + def formatPackageInstance(self, package: PackageInstantiation, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append( - "{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix) - ) - buffer.append( - "{prefix} Package: {name!s}".format( - prefix=prefix, name=package.PackageReference - ) - ) + buffer.append("{prefix}- Name: {name}".format(name=package.Identifier, prefix=prefix)) + buffer.append("{prefix} Package: {name!s}".format(prefix=prefix, name=package.PackageReference)) buffer.append("{prefix} Generic Map: ...".format(prefix=prefix)) # for item in package.GenericItems: # for line in self.formatGeneric(item, level + 1): @@ -342,14 +306,10 @@ class PrettyPrint: return buffer - def formatPackageBody( - self, packageBody: PackageBody, level: int = 0 - ) -> StringBuffer: + def formatPackageBody(self, packageBody: PackageBody, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append( - "{prefix}- Name: {name}".format(name=packageBody.Identifier, prefix=prefix) - ) + buffer.append("{prefix}- Name: {name}".format(name=packageBody.Identifier, prefix=prefix)) buffer.append("{prefix} Declared:".format(prefix=prefix)) for item in packageBody.DeclaredItems: for line in self.formatDeclaredItems(item, level + 1): @@ -357,31 +317,21 @@ class PrettyPrint: return buffer - def formatConfiguration( - self, configuration: Configuration, level: int = 0 - ) -> StringBuffer: + def formatConfiguration(self, configuration: Configuration, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append( - "{prefix}- Name: {name}".format( - name=configuration.Identifier, prefix=prefix - ) - ) + buffer.append("{prefix}- Name: {name}".format(name=configuration.Identifier, prefix=prefix)) return buffer def formatContext(self, context: Context, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append( - "{prefix}- Name: {name}".format(name=context.Identifier, prefix=prefix) - ) + buffer.append("{prefix}- Name: {name}".format(name=context.Identifier, prefix=prefix)) return buffer - def formatGeneric( - self, generic: Union[NamedEntity, GenericInterfaceItem], level: int = 0 - ) -> StringBuffer: + def formatGeneric(self, generic: Union[NamedEntity, GenericInterfaceItem], level: int = 0) -> StringBuffer: if isinstance(generic, GenericConstantInterfaceItem): return self.formatGenericConstant(generic, level) elif isinstance(generic, GenericTypeInterfaceItem): @@ -393,9 +343,7 @@ class PrettyPrint: ) ) - def formatPort( - self, port: Union[NamedEntity, PortInterfaceItem], level: int = 0 - ) -> StringBuffer: + def formatPort(self, port: Union[NamedEntity, PortInterfaceItem], level: int = 0) -> StringBuffer: if isinstance(port, PortSignalInterfaceItem): return self.formatPortSignal(port, level) else: @@ -405,9 +353,7 @@ class PrettyPrint: ) ) - def formatGenericConstant( - self, generic: GenericConstantInterfaceItem, level: int = 0 - ) -> StringBuffer: + def formatGenericConstant(self, generic: GenericConstantInterfaceItem, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level @@ -416,18 +362,14 @@ class PrettyPrint: prefix=prefix, name=", ".join(generic.Identifiers), mode=generic.Mode, - subtypeindication=self.formatSubtypeIndication( - generic.Subtype, "generic", generic.Identifiers[0] - ), + subtypeindication=self.formatSubtypeIndication(generic.Subtype, "generic", generic.Identifiers[0]), initialValue=self.formatInitialValue(generic), ) ) return buffer - def formatGenericType( - self, generic: GenericConstantInterfaceItem, level: int = 0 - ) -> StringBuffer: + def formatGenericType(self, generic: GenericConstantInterfaceItem, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level @@ -440,9 +382,7 @@ class PrettyPrint: return buffer - def formatPortSignal( - self, port: PortSignalInterfaceItem, level: int = 0 - ) -> StringBuffer: + def formatPortSignal(self, port: PortSignalInterfaceItem, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level @@ -451,9 +391,7 @@ class PrettyPrint: prefix=prefix, name=", ".join(port.Identifiers), mode=port.Mode, - subtypeindication=self.formatSubtypeIndication( - port.Subtype, "port", port.Identifiers[0] - ), + subtypeindication=self.formatSubtypeIndication(port.Subtype, "port", port.Identifiers[0]), initialValue=self.formatInitialValue(port), ) ) @@ -474,9 +412,7 @@ class PrettyPrint: "{prefix}- constant {name} : {subtype}{default}".format( prefix=prefix, name=", ".join(item.Identifiers), - subtype=self.formatSubtypeIndication( - item.Subtype, "constant", item.Identifiers[0] - ), + subtype=self.formatSubtypeIndication(item.Subtype, "constant", item.Identifiers[0]), default=default, ) ) @@ -485,9 +421,7 @@ class PrettyPrint: "{prefix}- shared variable {name} : {subtype}".format( prefix=prefix, name=", ".join(item.Identifiers), - subtype=self.formatSubtypeIndication( - item.Subtype, "shared variable", item.Identifiers[0] - ), + subtype=self.formatSubtypeIndication(item.Subtype, "shared variable", item.Identifiers[0]), ) ) elif isinstance(item, Signal): @@ -495,9 +429,7 @@ class PrettyPrint: "{prefix}- signal {name} : {subtype}{initValue}".format( prefix=prefix, name=", ".join(item.Identifiers), - subtype=self.formatSubtypeIndication( - item.Subtype, "signal", item.Identifiers[0] - ), + subtype=self.formatSubtypeIndication(item.Subtype, "signal", item.Identifiers[0]), initValue=" := {expr}".format(expr=str(item.DefaultExpression)) if item.DefaultExpression is not None else "", @@ -508,15 +440,11 @@ class PrettyPrint: "{prefix}- File {name} : {subtype}".format( prefix=prefix, name=", ".join(item.Identifiers), - subtype=self.formatSubtypeIndication( - item.Subtype, "file", item.Identifiers[0] - ), + subtype=self.formatSubtypeIndication(item.Subtype, "file", item.Identifiers[0]), ) ) elif isinstance(item, (FullType, IncompleteType)): - buffer.append( - "{prefix}- {type}".format(prefix=prefix, type=self.formatType(item)) - ) + buffer.append("{prefix}- {type}".format(prefix=prefix, type=self.formatType(item))) elif isinstance(item, Subtype): buffer.append( "{prefix}- subtype {name} is ?????".format( @@ -549,9 +477,7 @@ class PrettyPrint: buffer.append(line) elif isinstance(item, Attribute): buffer.append( - "{prefix}- attribute {name} : {type!s}".format( - prefix=prefix, name=item.Identifier, type=item.Subtype - ) + "{prefix}- attribute {name} : {type!s}".format(prefix=prefix, name=item.Identifier, type=item.Subtype) ) elif isinstance(item, AttributeSpecification): buffer.append( @@ -564,17 +490,9 @@ class PrettyPrint: ) ) elif isinstance(item, UseClause): - buffer.append( - "{prefix}- use {names}".format( - prefix=prefix, names=", ".join([str(n) for n in item.Names]) - ) - ) + buffer.append("{prefix}- use {names}".format(prefix=prefix, names=", ".join([str(n) for n in item.Names]))) elif isinstance(item, Package): - buffer.append( - "{prefix}- package {name} is ..... end package".format( - prefix=prefix, name=item.Identifier - ) - ) + buffer.append("{prefix}- package {name} is ..... end package".format(prefix=prefix, name=item.Identifier)) elif isinstance(item, PackageInstantiation): buffer.append( "{prefix}- package {name} is new {name2!s} generic map (.....)".format( @@ -582,17 +500,9 @@ class PrettyPrint: ) ) elif isinstance(item, DefaultClock): - buffer.append( - "{prefix}- default {name} is {expr}".format( - prefix=prefix, name=item.Identifier, expr="..." - ) - ) + buffer.append("{prefix}- default {name} is {expr}".format(prefix=prefix, name=item.Identifier, expr="...")) else: - raise PrettyPrintException( - "Unhandled declared item kind '{name}'.".format( - name=item.__class__.__name__ - ) - ) + raise PrettyPrintException("Unhandled declared item kind '{name}'.".format(name=item.__class__.__name__)) return buffer @@ -619,9 +529,7 @@ class PrettyPrint: elif isinstance(item, ProtectedTypeBody): result += "protected body ..... end protected body" else: - raise PrettyPrintException( - "Unknown type '{name}'".format(name=item.__class__.__name__) - ) + raise PrettyPrintException("Unknown type '{name}'".format(name=item.__class__.__name__)) return result @@ -633,9 +541,7 @@ class PrettyPrint: for constraint in subtypeIndication.Constraints: constraints.append(str(constraint)) - return "{type}({constraints})".format( - type=subtypeIndication.SymbolName, constraints=", ".join(constraints) - ) + return "{type}({constraints})".format(type=subtypeIndication.SymbolName, constraints=", ".join(constraints)) else: raise PrettyPrintException( "Unhandled subtype kind '{type}' for {entity} '{name}'.".format( @@ -649,23 +555,15 @@ class PrettyPrint: return " := {expr!s}".format(expr=item.DefaultExpression) - def formatHierarchy( - self, statement: ConcurrentStatement, level: int = 0 - ) -> StringBuffer: + def formatHierarchy(self, statement: ConcurrentStatement, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level if isinstance(statement, ProcessStatement): - buffer.append( - "{prefix}- {label}: process(...)".format( - prefix=prefix, label=statement.Label - ) - ) + buffer.append("{prefix}- {label}: process(...)".format(prefix=prefix, label=statement.Label)) elif isinstance(statement, EntityInstantiation): buffer.append( - "{prefix}- {label}: entity {name}".format( - prefix=prefix, label=statement.Label, name=statement.Entity - ) + "{prefix}- {label}: entity {name}".format(prefix=prefix, label=statement.Label, name=statement.Entity) ) elif isinstance(statement, ComponentInstantiation): buffer.append( @@ -680,9 +578,7 @@ class PrettyPrint: ) ) elif isinstance(statement, ConcurrentBlockStatement): - buffer.append( - "{prefix}- {label}: block".format(prefix=prefix, label=statement.Label) - ) + buffer.append("{prefix}- {label}: block".format(prefix=prefix, label=statement.Label)) for stmt in statement.Statements: for line in self.formatHierarchy(stmt, level + 2): buffer.append(line) @@ -709,11 +605,7 @@ class PrettyPrint: for line in self.formatHierarchy(stmt, level + 2): buffer.append(line) if statement.ElseBranch is not None: - buffer.append( - "{prefix} {label}: else generate".format( - prefix=prefix, label=statement.Label - ) - ) + buffer.append("{prefix} {label}: else generate".format(prefix=prefix, label=statement.Label)) for stmt in statement.ElseBranch.Statements: for line in self.formatHierarchy(stmt, level + 2): buffer.append(line) @@ -726,11 +618,7 @@ class PrettyPrint: ) ) for case in statement.Cases: - buffer.append( - "{prefix} {case!s}".format( - prefix=prefix, label=case.Label, case=case - ) - ) + buffer.append("{prefix} {case!s}".format(prefix=prefix, label=case.Label, case=case)) for stmt in case.Statements: for line in self.formatHierarchy(stmt, level + 2): buffer.append(line) |