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-rw-r--r--pyGHDL/dom/DesignUnit.py1
-rw-r--r--pyGHDL/dom/__init__.py1
2 files changed, 1 insertions, 1 deletions
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index a8249d38d..c4f19deef 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -59,6 +59,7 @@ from pyVHDLModel.VHDLModel import (
PortInterfaceItem,
EntityOrSymbol,
Name,
+ ConcurrentStatement,
)
from pyGHDL.libghdl.vhdl import nodes
diff --git a/pyGHDL/dom/__init__.py b/pyGHDL/dom/__init__.py
index 19f23a94b..d3dc506f5 100644
--- a/pyGHDL/dom/__init__.py
+++ b/pyGHDL/dom/__init__.py
@@ -46,7 +46,6 @@ __all__ = []
@export
class Position:
"""Represents the source code position of a IIR node in a source file."""
-
_filename: Path
_line: int
_column: int