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-rw-r--r--pyGHDL/dom/Expression.py74
1 files changed, 74 insertions, 0 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index 80ef2823c..fec347b57 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -30,6 +30,20 @@
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
+from typing import List
+
+from pyGHDL.dom.Aggregates import (
+ OthersAggregateElement,
+ SimpleAggregateElement,
+ RangedAggregateElement,
+ IndexedAggregateElement,
+ NamedAggregateElement,
+)
+from pyGHDL.dom.Symbol import EnumerationLiteralSymbol
+from pyGHDL.libghdl import utils
+
+from pyGHDL.dom.Common import DOMException
+from pyGHDL.dom._Utils import GetIirKindOfNode
from pyGHDL.libghdl.vhdl import nodes
from pydecor import export
@@ -38,6 +52,7 @@ from pyVHDLModel.VHDLModel import (
IdentityExpression as VHDLModel_IdentityExpression,
NegationExpression as VHDLModel_NegationExpression,
AbsoluteExpression as VHDLModel_AbsoluteExpression,
+ ParenthesisExpression as VHDLModel_ParenthesisExpression,
TypeConversion as VHDLModel_TypeConversion,
FunctionCall as VHDLModel_FunctionCall,
QualifiedExpression as VHDLModel_QualifiedExpression,
@@ -66,7 +81,9 @@ from pyVHDLModel.VHDLModel import (
ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression,
RotateRightExpression as VHDLModel_RotateRightExpression,
RotateLeftExpression as VHDLModel_RotateLeftExpression,
+ Aggregate as VHDLModel_Aggregate,
Expression,
+ AggregateElement,
)
__all__ = []
@@ -120,6 +137,20 @@ class AbsoluteExpression(VHDLModel_AbsoluteExpression, _ParseUnaryExpression):
@export
+class ParenthesisExpression(VHDLModel_ParenthesisExpression, _ParseUnaryExpression):
+ def __init__(self, operand: Expression):
+ super().__init__()
+ self._operand = operand
+
+ @classmethod
+ def parse(cls, node):
+ from pyGHDL.dom._Translate import GetExpressionFromNode
+
+ operand = GetExpressionFromNode(nodes.Get_Expression(node))
+ return cls(operand)
+
+
+@export
class TypeConversion(VHDLModel_TypeConversion):
def __init__(self, operand: Expression):
super().__init__()
@@ -350,3 +381,46 @@ class RotateLeftExpression(VHDLModel_RotateLeftExpression, _ParseBinaryExpressio
super().__init__()
self._leftOperand = left
self._rightOperand = right
+
+
+@export
+class Aggregate(VHDLModel_Aggregate):
+ def __init__(self, elements: List[AggregateElement]):
+ super().__init__()
+ self._elements = elements
+
+ @classmethod
+ def parse(cls, node):
+ from pyGHDL.dom._Translate import GetExpressionFromNode
+
+ choices = []
+
+ choicesChain = nodes.Get_Association_Choices_Chain(node)
+ for item in utils.chain_iter(choicesChain):
+ kind = GetIirKindOfNode(item)
+ if kind == nodes.Iir_Kind.Choice_By_None:
+ value = GetExpressionFromNode(nodes.Get_Associated_Expr(item))
+ choices.append(SimpleAggregateElement(value))
+ elif kind == nodes.Iir_Kind.Choice_By_Expression:
+ index = GetExpressionFromNode(nodes.Get_Choice_Expression(item))
+ value = GetExpressionFromNode(nodes.Get_Associated_Expr(item))
+ choices.append(IndexedAggregateElement(index, value))
+ elif kind == nodes.Iir_Kind.Choice_By_Range:
+ r = GetExpressionFromNode(nodes.Get_Choice_Range(item))
+ value = GetExpressionFromNode(nodes.Get_Associated_Expr(item))
+ choices.append(RangedAggregateElement(r, value))
+ elif kind == nodes.Iir_Kind.Choice_By_Name:
+ name = EnumerationLiteralSymbol(nodes.Get_Choice_Name(item))
+ value = GetExpressionFromNode(nodes.Get_Associated_Expr(item))
+ choices.append(NamedAggregateElement(name, value))
+ elif kind == nodes.Iir_Kind.Choice_By_Others:
+ expression = None
+ choices.append(OthersAggregateElement(expression))
+ else:
+ raise DOMException(
+ "Unknown choice kind '{kindName}'({kind}) in aggregate '{aggr}'.".format(
+ kind=kind, kindName=kind.name, aggr=node
+ )
+ )
+
+ return cls(choices)