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Diffstat (limited to 'doc')
44 files changed, 3510 insertions, 2 deletions
diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst index baf6c6a52..4cbbe8027 100644 --- a/doc/using/QuickStartGuide.rst +++ b/doc/using/QuickStartGuide.rst @@ -52,7 +52,31 @@ To illustrate the large purpose of `VHDL`, here is a commented `'Hello world'` p * As a result, :option:`-r` is just a passthrough to the binary generated in the `elaboration`. Therefore, the executable can be run directly, :samp:`./hello_world`. See :option:`-r` for more informartion. .. HINT:: :option:`-e` can be bypassed with mcode, since :option:`-r` actually elaborates the design and saves it on memory before running the simulation. But you can still use it to check for some elaboration problems. - + +The `heartbeat` program +======================= + +.. code-block:: VHDL + + entity hello_world is + port ( clk: out std_logic; ) + end hearbeat; + + architecture behaviour of hello_world is + begin + -- Clock process definition + clk_process: process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + end behaviour; + +.. TODO:: Complete `heartbeat` example program + + A full adder ============ @@ -204,4 +228,5 @@ Further examples .. TODO:: * Add references to examples/tutorials with GHDL. - * Shall `René Doß <https://mail.gna.org/public/ghdl-discuss/2017-01/msg00000.html>` want to contribute adapting his article to RST?
\ No newline at end of file + * Shall `René Doß <https://mail.gna.org/public/ghdl-discuss/2017-01/msg00000.html>` want to contribute adapting his article to RST? + * https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki
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b/doc/using/UART_srcs/capitalisation/capitalisation.vhd @@ -0,0 +1,51 @@ +-- loopback engine +---------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +entity capitalisation is + port( + clk : in std_logic; + reset : in std_logic; + --in + rdata : in std_logic_vector(7 downto 0); + rd_en : in std_logic; + rd : out std_logic; + --out + wdata : out std_logic_vector(7 downto 0); + wr_en : in std_logic; + wr : out std_logic + ); +end; + +architecture Behavioral of capitalisation is + + + +begin + + + process(clk) + begin + wr<='0'; + rd<='0'; + if wr_en='1' and rd_en ='1' then + wr<='1'; + rd<='1'; + if (unsigned(rdata)>X"60") and + (unsigned(rdata)<X"7B") then + wdata<=rdata(7 downto 6 )&'0'& rdata(4 downto 0); + else + wdata<=rdata; + end if; + end if; + if reset='1' then + wr<='0'; + end if; + end process; + + + +end Behavioral; + diff --git a/doc/using/UART_srcs/capitalisation/makefile b/doc/using/UART_srcs/capitalisation/makefile new file mode 100644 index 000000000..ad8a01b04 --- /dev/null +++ b/doc/using/UART_srcs/capitalisation/makefile @@ -0,0 +1,18 @@ +all: + rm -rf work + mkdir work + + ghdl -a --work=work --workdir=work top_capitalisation.vhd + ghdl -a --work=work --workdir=work capitalisation.vhd + ghdl -a --work=work --workdir=work ../rx/UART_RX_8N1.vhd + ghdl -a --work=work --workdir=work ../tx/UART_TX_8N1.vhd + ghdl -a --work=work --workdir=work capitalisation.vhd + + ghdl -a --work=work --workdir=work tb_capitalisation.vhd + ghdl -e --workdir=work -Pwork tb_capitalisation + ghdl -r tb_capitalisation --wave=tbench.ghw --stop-time=700us + + +view: + gtkwave tbench.ghw a.gtkw + diff --git a/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd b/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd new file mode 100644 index 000000000..364142946 --- /dev/null +++ b/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd @@ -0,0 +1,89 @@ +-- tb_capitalisation.vhd +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_capitalisation is +end tb_capitalisation; + +architecture behavior of tb_capitalisation is + + constant board_clk_period : time := 10 ns; + constant board_clk_freq: integer :=100E6; --100MHz + + signal board_clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal rx : std_logic := '1'; + signal tx : std_logic; + + procedure tx_char (signal txpin : out std_logic; + txdata : in character; baudrate : in integer) is + constant bittime : time := (integer(1000000000.0/real(baudrate))) * 1 ns; + variable c : std_logic_vector(7 downto 0); + begin + c := std_logic_vector(to_unsigned(character'pos(txdata), 8)); + txpin <= '0'; -- Startbit + wait for bittime; + for i in 0 to 7 loop + txpin <= c(i); + wait for bittime; + end loop; + txpin <= '1'; -- Stopbit + wait for bittime; + end tx_char; + + -- Component Declaration for the Unit Under Test (UUT) +component top_capitalisation is + generic (clk_freq : integer; + baudrate : integer); + port( + board_clk : in std_logic ; + reset : in std_logic ; + rx : in std_logic ; + tx : out std_logic ); +end component; + +begin + -- Instantiate the Unit Under Test (UUT) +UART_example: top_capitalisation + generic map ( + clk_freq => board_clk_freq, + baudrate =>115200) + port map( + board_clk => board_clk, + reset => reset, + rx => rx, + tx => tx ); + + process + begin + wait for 80000 ns; + tx_char(RX, '$', 115200); + tx_char(RX, 'g', 115200); + tx_char(RX, '#', 115200); + wait for 50 us; + tx_char(RX, 'b', 115200); + tx_char(RX, 'c', 115200); + wait; -- will wait forever + end process; + + -- Clock process definitions + board_clk_process : process + begin + board_clk <= '0'; + wait for board_clk_period/2; + board_clk <= '1'; + wait for board_clk_period/2; + end process; + + -- Stimulus process + process + begin + reset <= '1'; + wait for 100 ns; + reset <='0'; + wait; + end process; + +end; diff --git a/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd b/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd new file mode 100644 index 000000000..01c8e3585 --- /dev/null +++ b/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd @@ -0,0 +1,126 @@ +-- top_capitalisation.vhd +---------------------------------------------------------------------- + +-- top_capitalisation +-- | +-- + capitalisation +-- + UART_8N1_RX +-- + UART_8N1_TX + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity top_capitalisation is + generic (clk_freq : integer; + baudrate : integer); + port( + board_clk : in std_logic ; + reset : in std_logic ; + rx : in std_logic ; + tx : out std_logic ); +end top_capitalisation; + +architecture behavior of top_capitalisation is + signal rd_en : std_logic; + signal rdata : std_logic_vector (7 downto 0); + signal rd : std_logic; + + signal wr_en : std_logic; + signal wdata : std_logic_vector (7 downto 0); + signal wr : std_logic; + +component capitalisation is + port( + clk : in std_logic; + reset : in std_logic; + --in + rdata : in std_logic_vector(7 downto 0); + rd_en : in std_logic; + rd : out std_logic; + --out + wdata : out std_logic_vector(7 downto 0); + wr_en : in std_logic; + wr : out std_logic + ); +end component; + +component UART_8N1_RX is + generic (clk_freq : integer; + baudrate : integer); + port( + clk : in std_logic; + reset : in std_logic; + --8bit interface + rdata : out std_logic_vector(7 downto 0); + rd : in std_logic; + rd_en : out std_logic; + --physical wire RX + rx : in std_logic + ); +end component; + +component UART_8N1_TX is + generic( + clk_freq : integer; + baudrate : integer; + addr_depth : integer:=5); + port( + clk : in std_logic; + reset : in std_logic; + --8bit interface + wdata : in std_logic_vector(7 downto 0); + wr : in std_logic; + wr_en : out std_logic; + + --physical wire + tx : out std_logic); +end component; + + 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sodipodi:role="line" + id="tspan4519" + x="110.25892" + y="516.77045">board_clk</tspan></text> + <text + xml:space="preserve" + style="font-style:normal;font-weight:normal;font-size:25px;line-height:125%;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" + x="114.15372" + y="548.17877" + id="text4521" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan4523" + x="114.15372" + y="548.17877">reset</tspan></text> + <path + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker5229)" + d="m 58.131259,544.64792 40.588544,0" + id="path5227" + inkscape:connector-curvature="0" /> + <path + inkscape:connector-curvature="0" + id="path5515" + d="m 58.131259,508.64792 40.588544,0" + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker5517)" /> + </g> +</svg> diff --git a/doc/using/UART_srcs/file_in_out/makefile b/doc/using/UART_srcs/file_in_out/makefile new file mode 100644 index 000000000..e7ee72400 --- /dev/null +++ b/doc/using/UART_srcs/file_in_out/makefile @@ -0,0 +1,13 @@ +all: + rm -rf work + mkdir work + + ghdl -a --work=work --workdir=work ../capitalisation/capitalisation.vhd + ghdl -a --work=work --workdir=work tb_file.vhd + ghdl -e --ieee=synopsys -fexplicit --workdir=work -Pwork tb_file + ghdl -r tb_file --wave=tbench.ghw --stop-time=200us + + +view: + gtkwave tbench.ghw a.gtkw + diff --git a/doc/using/UART_srcs/file_in_out/tb_file.vhd b/doc/using/UART_srcs/file_in_out/tb_file.vhd new file mode 100644 index 000000000..fe18f6665 --- /dev/null +++ b/doc/using/UART_srcs/file_in_out/tb_file.vhd @@ -0,0 +1,142 @@ +--tb_file.vhd +------------------------------------------------------------------------ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY tb_file IS +END tb_file; +--vhdl no seek or rewind function in VHDL + +ARCHITECTURE behavior OF tb_file IS + +signal clk : std_logic := '0'; +signal reset : std_logic; + +signal rdata : std_logic_vector(7 downto 0); +signal rd_en : std_logic; +signal rd : std_logic; + +signal wdata : std_logic_vector(7 downto 0); +signal wr_en : std_logic:='1'; +signal wr : std_logic; + + -- Component Declaration for the Unit Under Test (UUT) +component capitalisation is + port( + clk : in std_logic; + reset : in std_logic; + --in + rdata : in std_logic_vector(7 downto 0); + rd_en : in std_logic; + rd : out std_logic; + --out + wdata : out std_logic_vector(7 downto 0); + wr_en : in std_logic; + wr : out std_logic + ); +end component; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +subtype by_te is character; +type f_byte is file of by_te; + +BEGIN + +process(clk) +begin + if rising_edge (clk) then + if reset='0' then + wr_en<='1'; + else + wr_en<='0'; + end if; + end if; +end process; + +--read a file +process (reset,clk) +constant file_name: string:="test.txt"; +file in_file: f_byte open read_mode is file_name; + +variable a:character; + +begin + if reset='1' then + rd_en<='0'; + else + + if rising_edge(clk) then + if rd_en='0' or rd='1' then + if not endfile (in_file) then + read(in_file,a); + rdata<=std_logic_vector(to_unsigned(character'pos(a),8)); + --very tricky the conversation + rd_en<='1'; + else + rd_en<='0'; + end if; + end if; + end if; + --wait until rising_edge(CLK) and rd='1'; + end if; +end process; + + + +--write a file +process (clk) +constant file_name: string:="test1.txt"; +file out_file: f_byte open write_mode is file_name; + +----variable in_line,out_line: line; +variable b:character; + + begin + if rising_edge(CLK) then + if reset='0' then + if wr='1' then + b:=character'val(to_integer(unsigned(wdata))); + write(out_file,b); + end if; + end if; + end if; + end process; + + stim_proc : process + begin + reset <= '1'; + + wait for 50 ns; + reset <='0'; + + wait; + end process; + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + +engine: capitalisation + port map( + + clk => clk, + reset => reset, + + rdata => rdata, + rd_en => rd_en, + rd => rd, + + wdata => wdata, + wr_en => wr_en, + wr => wr + ); + + +END; diff --git a/doc/using/UART_srcs/file_in_out/test.txt b/doc/using/UART_srcs/file_in_out/test.txt new file mode 100644 index 000000000..3ee58d9a3 --- /dev/null +++ b/doc/using/UART_srcs/file_in_out/test.txt @@ -0,0 +1 @@ +Hallo world! Can you see my text? diff --git a/doc/using/UART_srcs/file_in_out/test1.txt b/doc/using/UART_srcs/file_in_out/test1.txt new file mode 100644 index 000000000..a868f3f93 --- /dev/null +++ b/doc/using/UART_srcs/file_in_out/test1.txt @@ -0,0 +1 @@ +HALLO WORLD! CAN YOU SEE MY TEXT? diff --git a/doc/using/UART_srcs/file_in_out/zeichnung.png b/doc/using/UART_srcs/file_in_out/zeichnung.png Binary files differnew file mode 100644 index 000000000..e849417f4 --- /dev/null +++ b/doc/using/UART_srcs/file_in_out/zeichnung.png diff --git a/doc/using/UART_srcs/rx/UART_RX_8N1.vhd b/doc/using/UART_srcs/rx/UART_RX_8N1.vhd new file mode 100644 index 000000000..a7fe757a5 --- /dev/null +++ b/doc/using/UART_srcs/rx/UART_RX_8N1.vhd @@ -0,0 +1,150 @@ +-- UART_RX_8N1.vhd +---------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + + +entity UART_8N1_RX is + + generic (clk_freq : integer; + baudrate : integer); + port( + clk : in std_logic; + reset : in std_logic; + --8bit interface + rdata : out std_logic_vector(7 downto 0); + rd : in std_logic; + rd_en : out std_logic; + --physical wire RX + rx : in std_logic + ); +end UART_8N1_RX; + + +architecture Behavioral of UART_8N1_RX is + + type state_type is (idle, start, data0, data1, data2, data3, data4, + data5, data6, data7, stop); + signal state : state_type; + + signal puffer : std_logic_vector (7 downto 0); + +--FIFO + type RAM is array (0 to 63) of std_logic_vector (7 downto 0); + + signal fifo : RAM ; + + signal nextwrite : unsigned(5 downto 0); + signal nextread : unsigned(5 downto 0); + + constant tick : integer := clk_freq/baudrate; + signal tick_counter : integer range 0 to (tick+1); + + +begin + + rdata <= fifo(to_integer(nextread)); + + process (clk) + begin + if rising_edge(clk) then + if rd = '1' then + nextread <= nextread+1; + end if; + if reset = '1' then + nextread <= (others => '0'); + end if; + end if; + end process; + + rd_en<= '0' when nextread=nextwrite else '1'; + + + process(clk) + begin + + if (clk'event and clk = '1') then + tick_counter <= tick_counter + 1; + + case state is + + when idle => + tick_counter <= 0; + if (rx = '0') then --check start condtion + state <= start; + else + state <= idle; + end if; + + when start => + if (tick_counter = tick/2) then --capture in the middle + tick_counter <= 0; + state <= data0; + end if; + + when data0 => + if (tick_counter = tick) then + puffer (0) <= rx; + tick_counter <= 0; + state <= data1; + end if; + when data1 => + if (tick_counter = tick) then + puffer (1) <= rx; + tick_counter <= 0; + state <= data2; + end if; + when data2 => + if (tick_counter = tick) then + puffer (2) <= rx; + tick_counter <= 0; + state <= data3; + end if; + when data3 => + if (tick_counter = tick) then + puffer(3) <= rx; + tick_counter <= 0; + state <= data4; + end if; + when data4 => + if (tick_counter = tick) then + puffer (4) <= rx; + tick_counter <= 0; + state <= data5; + end if; + when data5 => + if (tick_counter = tick) then + puffer (5) <= rx; + tick_counter <= 0; + state <= data6; + end if; + when data6 => + if (tick_counter = tick) then + puffer (6) <= rx; + tick_counter <= 0; + state <= data7; + end if; + when data7 => + if (tick_counter = tick) then + puffer (7) <= rx; + tick_counter <= 0; + state <= stop; + end if; + when stop => + if (tick_counter = tick) then + fifo(to_integer(nextwrite)) <= puffer; + nextwrite <= nextwrite+1; + tick_counter <= 0; + state <= idle; + end if; + end case; + if reset='1' then + state <=idle; + nextwrite <= (others => '0'); + end if; + end if; + + end process; +end Behavioral; + diff --git a/doc/using/UART_srcs/rx/makefile b/doc/using/UART_srcs/rx/makefile new file mode 100644 index 000000000..3546a42ad --- /dev/null +++ b/doc/using/UART_srcs/rx/makefile @@ -0,0 +1,8 @@ + +all: + ghdl -i *.vhd + ghdl -m tb_UART_RX_8N1 + ghdl -r tb_UART_RX_8N1 --stop-time=800us --wave=RX.ghw + +view: + gtkwave RX.ghw diff --git a/doc/using/UART_srcs/rx/sim_RX.png b/doc/using/UART_srcs/rx/sim_RX.png Binary files differnew file mode 100644 index 000000000..5062d26a3 --- /dev/null +++ b/doc/using/UART_srcs/rx/sim_RX.png diff --git a/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd b/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd new file mode 100644 index 000000000..4fd67c8e7 --- /dev/null +++ b/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd @@ -0,0 +1,121 @@ +-- tb_UART_RX_8N1.vhd +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity tb_UART_RX_8N1 is +end tb_UART_RX_8N1; + +architecture behavior of tb_UART_RX_8N1 is + + signal board_clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal rx : std_logic := '1'; + signal rd : std_logic := '0'; + signal rd_en : std_logic; + signal data : std_logic_vector (7 downto 0); + + procedure tx_char (signal txpin : out std_logic; + txdata : in character; baudrate : in integer) is + constant bittime : time := (integer(1000000000.0/real(baudrate))) * 1 ns; + variable c : std_logic_vector(7 downto 0); + begin + c := std_logic_vector(to_unsigned(character'pos(txdata), 8)); + txpin <= '0'; -- Startbit + wait for bittime; + for i in 0 to 7 loop + txpin <= c(i); + wait for bittime; + end loop; + txpin <= '1'; -- Stopbit + wait for bittime; + end tx_char; + --Outputs + +component UART_8N1_RX is + + generic (clk_freq : integer; + baudrate : integer); + port( + clk : in std_logic; + reset : in std_logic; + --8bit interface + rdata : out std_logic_vector(7 downto 0); + rd : in std_logic; + rd_en : out std_logic; + --physical wire RX + rx : in std_logic + ); +end component; + + constant board_clk_period : time := 10 ns; + constant board_clk_freq: integer :=100E6; --100MHz + +begin + + -- Instantiate the Unit Under Test (UUT) +UART_RX:UART_8N1_RX + + generic map ( + clk_freq => board_clk_freq, + baudrate =>115200) + port map( + clk => board_clk, + reset => reset, + rdata => data, + rd => rd, + rd_en => rd_en, + --physical wire RX + rx => rx + ); + + process + begin + wait for 80000 ns; + tx_char(RX, '$', 115200); + tx_char(RX, 'g', 115200); + tx_char(RX, '#', 115200); + wait for 50 us; + tx_char(RX, '6', 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downto 0); + wr : in std_logic; + wr_en : out std_logic; + + --physical wire + tx : out std_logic); +end; + + +architecture Behavioral of UART_8N1_TX is +--FSM + type state_type is (idle, start, data0, data1, data2, data3, data4, + data5, data6, data7, stop); + + signal state : state_type := idle; + signal nextstate : state_type := idle; + + --FIFO + type RAM is array (0 to (2**(addr_depth)-1)) of std_logic_vector (7 downto 0); + signal fifo : RAM; + signal nextwrite : unsigned((addr_depth-1) downto 0); + signal nextread : unsigned((addr_depth-1) downto 0); + + signal send_empty: std_logic; + + --output + signal data_tx : std_logic_vector (7 downto 0); + constant tick : integer := (clk_freq/baudrate); + signal tick_counter : integer range 0 to (tick+1); + +begin + + wr_en <= '0' when (nextwrite+1 = nextread) else '1'; + send_empty<='1' when nextwrite=nextread else '0'; + + process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + nextread <= (others => '0'); + elsif state = stop and nextstate = idle then + nextread <= nextread+1; + end if; + end if; + end process; + + process(clk) + begin + if rising_edge(clk) then + state <= nextstate; + end if; + end process; + + process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + nextwrite <= (others => '0'); + elsif wr = '1' then + fifo(to_integer(nextwrite)) <= wdata; + nextwrite <= nextwrite+1; + + end if; + end if; + end process; + + + data_tx <= fifo(to_integer(nextread)); + + process(clk) + begin + if rising_edge(clk) then + if state = idle then + if nextwrite /= nextread then + nextstate <= start; + tick_counter <= 0; + tx <= '0'; + else + tx <= '1'; + end if; + else + if tick_counter = tick then + tick_counter <= 0; + else + tick_counter <= tick_counter + 1; + end if; + end if; + if tick_counter = tick then + if state = start then + nextstate <= data0; + tx <= data_tx(0); + end if; + + if state = data0 then + nextstate <= data1; + tx <= data_tx(1); + end if; + + if state = data1 then + nextstate <= data2; + tx <= data_tx(2); + end if; + + if state = data2 then + nextstate <= data3; + tx <= data_tx(3); + end if; + if state = data3 then + nextstate <= data4; + tx <= data_tx(4); + end if; + if state = data4 then + nextstate <= data5; + tx <= data_tx(5); + end if; + if state = data5 then + nextstate <= data6; + tx <= data_tx(6); + end if; + if state = data6 then + nextstate <= data7; + tx <= data_tx(7); + end if; + if state = data7 then + nextstate <= stop; + tx <= '1'; + end if; + if state = stop then + nextstate <= idle; + tx <= '1'; + end if; + end if; + + if reset = '1' then + tick_counter <= 0; + tx <= '1'; + nextstate <= idle; + end if; + end if; + + end process; + + +end Behavioral; + diff --git a/doc/using/UART_srcs/tx/makefile b/doc/using/UART_srcs/tx/makefile new file mode 100644 index 000000000..83168f2f1 --- /dev/null +++ b/doc/using/UART_srcs/tx/makefile @@ -0,0 +1,8 @@ + +all: + ghdl -i *.vhd + ghdl -m tb_UART_TX_8N1 + ghdl -r tb_UART_TX_8N1 --stop-time=200us --wave=TX.ghw + +view: + gtkwave TX.ghw diff --git a/doc/using/UART_srcs/tx/path6054.png b/doc/using/UART_srcs/tx/path6054.png Binary files differnew file mode 100644 index 000000000..d2c657243 --- /dev/null +++ b/doc/using/UART_srcs/tx/path6054.png diff --git a/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd b/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd new file mode 100644 index 000000000..a485a404a --- /dev/null +++ b/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd @@ -0,0 +1,95 @@ +-- tb_UART_TX_8N1.vhd +---------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_UART_TX_8N1 is +end tb_UART_TX_8N1; + +architecture behavior of tb_UART_TX_8N1 is + + --Inputs + signal board_clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal send_data : std_logic_vector (7 downto 0); + signal wr : std_logic := '0'; + signal tx : std_logic; + + -- Component Declaration for the Unit Under Test (UUT) + component UART_8N1_TX is + generic( + clk_freq : integer; + baudrate : integer; + addr_depth : integer:=5); + port( + clk : in std_logic; + reset : in std_logic; + --8bit interface + wdata : in std_logic_vector(7 downto 0); + wr : in std_logic; + wr_en : out std_logic; + + --physical wire + tx : out std_logic); +end component; + + constant board_clk_period : time := 10 ns; + constant board_clk_freq: integer :=100E6; --100MHz + +begin + + -- Instantiate the Unit Under Test (UUT) +UART_TX: UART_8N1_TX + generic map( + clk_freq => board_clk_freq, + baudrate => 115200 + -- addr_depth => use predefined + ) + port map( + clk => board_clk, + reset => reset, + + wdata => send_data, + wr => wr, + wr_en => open, + + tx => tx + ); + + -- Clock process definitions + board_clk_process : process + begin + board_clk <= '0'; + wait for board_clk_period/2; + board_clk <= '1'; + wait for board_clk_period/2; + end process; + + + -- Stimulus process + stim_proc : process + begin + reset <= '1'; + + wait for 15 us; + reset <='0'; + send_data<=X"A0"; + wait until rising_edge(board_clk); + wr<= '1'; + + wait until rising_edge(board_clk); + wr<= '0'; + + wait for 5 us; + + wait until rising_edge(board_clk); + wr<= '1'; + send_data<=X"B1"; + + wait until rising_edge(board_clk); + wr<= '0'; + wait; + end process; + + end; diff --git a/doc/using/UART_srcs/tx/tx.gtkw b/doc/using/UART_srcs/tx/tx.gtkw new file mode 100644 index 000000000..92e8cd730 --- /dev/null +++ b/doc/using/UART_srcs/tx/tx.gtkw @@ -0,0 +1,33 @@ +[*] +[*] GTKWave Analyzer v3.3.67 (w)1999-2015 BSI +[*] Fri Dec 16 19:12:23 2016 +[*] +[dumpfile] "/home/red/artikel_uart/tx/TX.ghw" +[dumpfile_mtime] "Fri Dec 16 19:08:11 2016" +[dumpfile_size] 349946 +[savefile] "/home/red/artikel_uart/tx/tx.gtkw" +[timestart] 0 +[size] 1920 1016 +[pos] -83 -83 +*-35.000000 106965000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.tb_uart_tx_8n1. +[treeopen] top.tb_uart_tx_8n1.uart_tx. +[sst_width] 218 +[signals_width] 142 +[sst_expanded] 1 +[sst_vpaned_height] 215 +@28 +top.tb_uart_tx_8n1.board_clk +top.tb_uart_tx_8n1.reset +[color] 5 +top.tb_uart_tx_8n1.wr +@22 +#{top.tb_uart_tx_8n1.send_data[7:0]} top.tb_uart_tx_8n1.send_data[7] top.tb_uart_tx_8n1.send_data[6] top.tb_uart_tx_8n1.send_data[5] top.tb_uart_tx_8n1.send_data[4] top.tb_uart_tx_8n1.send_data[3] top.tb_uart_tx_8n1.send_data[2] top.tb_uart_tx_8n1.send_data[1] top.tb_uart_tx_8n1.send_data[0] +@200 +-FIFO_Control +@22 +#{top.tb_uart_tx_8n1.uart_tx.nextread[4:0]} top.tb_uart_tx_8n1.uart_tx.nextread[4] top.tb_uart_tx_8n1.uart_tx.nextread[3] top.tb_uart_tx_8n1.uart_tx.nextread[2] top.tb_uart_tx_8n1.uart_tx.nextread[1] top.tb_uart_tx_8n1.uart_tx.nextread[0] +#{top.tb_uart_tx_8n1.uart_tx.nextwrite[4:0]} top.tb_uart_tx_8n1.uart_tx.nextwrite[4] top.tb_uart_tx_8n1.uart_tx.nextwrite[3] top.tb_uart_tx_8n1.uart_tx.nextwrite[2] top.tb_uart_tx_8n1.uart_tx.nextwrite[1] top.tb_uart_tx_8n1.uart_tx.nextwrite[0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/doc/using/UART_srcs/uart.aux b/doc/using/UART_srcs/uart.aux new file mode 100644 index 000000000..d5ba29b80 --- /dev/null +++ b/doc/using/UART_srcs/uart.aux @@ -0,0 +1,48 @@ +\relax +\providecommand\hyper@newdestlabel[2]{} +\providecommand\HyperFirstAtBeginDocument{\AtBeginDocument} +\HyperFirstAtBeginDocument{\ifx\hyper@anchor\@undefined +\global\let\oldcontentsline\contentsline +\gdef\contentsline#1#2#3#4{\oldcontentsline{#1}{#2}{#3}} +\global\let\oldnewlabel\newlabel +\gdef\newlabel#1#2{\newlabelxx{#1}#2} +\gdef\newlabelxx#1#2#3#4#5#6{\oldnewlabel{#1}{{#2}{#3}}} +\AtEndDocument{\ifx\hyper@anchor\@undefined +\let\contentsline\oldcontentsline +\let\newlabel\oldnewlabel +\fi} +\fi} +\global\let\hyper@last\relax +\gdef\HyperFirstAtBeginDocument#1{#1} +\providecommand\HyField@AuxAddToFields[1]{} +\providecommand\HyField@AuxAddToCoFields[2]{} +\@writefile{toc}{\contentsline {section}{\numberline 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+\BOOKMARK [1][-]{section.2}{advanced TX Unit with FIFO}{}% 2 +\BOOKMARK [1][-]{section.3}{advanced RX Unit with FIFO}{}% 3 +\BOOKMARK [1][-]{section.4}{example application}{}% 4 +\BOOKMARK [1][-]{section.5}{Makefile for workflow}{}% 5 +\BOOKMARK [1][-]{section.6}{file in/out}{}% 6 +\BOOKMARK [1][-]{section.7}{VHPI Interface to an other language}{}% 7 +\BOOKMARK [1][-]{section.8}{closing words}{}% 8 diff --git a/doc/using/UART_srcs/uart.tex b/doc/using/UART_srcs/uart.tex new file mode 100644 index 000000000..1c1f21e20 --- /dev/null +++ b/doc/using/UART_srcs/uart.tex @@ -0,0 +1,269 @@ +\documentclass[a4paper,11pt]{article} +\usepackage[T1]{fontenc} +\usepackage[utf8]{inputenc} +\usepackage{lmodern} +%\usepackage{ngerman} +\usepackage{graphicx} +\usepackage{float} +\usepackage{attachfile} +\usepackage[T1]{fontenc} +%\usepackage{beramono}% monospaced font with bold variant + +\usepackage{listings} +\lstdefinelanguage{VHDL}{ + morekeywords={ + library,use,all,entity,is,port,in,out,end,architecture,of, + begin,and,generic,process,if,then,elsif,else,when, + signal, integer,std_logic,unsigned,signed,std_logic_vector, + constant, variable, wait, for, until, map + }, + morecomment=[l]-- +} + +\usepackage{xcolor} +\colorlet{keyword}{blue!100!black!80} +\colorlet{comment}{green!90!black!90} +\lstdefinestyle{vhdl}{ + language = VHDL, + basicstyle = \ttfamily\scriptsize, + keywordstyle = \color{keyword}\bfseries, + commentstyle = \color{comment} +} + +\lstdefinestyle{c}{ + language = c, + basicstyle = \ttfamily\scriptsize, + keywordstyle = \color{keyword}\bfseries, + commentstyle = \color{comment} +} + +\usepackage{hyperref} %remove the red boxes at contents +\hypersetup{colorlinks=true,linkcolor=black} + +\usepackage{fancyvrb} + +\setlength{\parindent}{0em} + + +\title{How to simulate an UART VHDL code with ghdl} +\author{René Doß \\ info@dossmatik.de} + +\begin{document} + +\maketitle +\tableofcontents + +\begin{abstract} +This article was written to demonstrate on a practical example how ghdl works. The reader should have basic knowledge about VHDL. This example is fitable code into a FPGA. The code is written vendor independent. UART as example is generally understandable and also parctical on many applications. +An asynchronous serial transmission has two parts Receiver and Transmitter. The handling is typical integrated on all microcontrollers today. Different sensors can communicate over UART. This makes this data transmission very interesting for a hardware developer. The Receiver and Transmitter code is included with an integrated FIFO. These all are demonstrated with ghdl simulation. You will get new spirit for VHDL code validation. The VHDL files are attached in this document. +\end{abstract} + +\newpage +\section{introduction UART transmission} +The signal is at silence condition high. A low on line manifests a start of transmission, followed by a number of data bits. The data bits are send from least significant bit (LSB) to most significant bit (MSB). Next bit is a high, witch is called stop bit and it is needed to mark the end of transmission. In this state a new start bit can be correct capture by the receiver. Note that no clock signal has sent through the serial line. The transmitter resynchronize on the falling edge in start bit condition. The data speed and the data length of sender an receiver have to be the same. +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.5]{UART_timing.png} + \caption{UART Timing} + \label{fig:UART Timing} + \end{center} +\end{figure} + +The baudrate specifies the transmission speed. The unit is baud bit per second. Common baudrates are established. +Internally the hardware of UART runs in higher clock rate. + +\section{advanced TX Unit with FIFO} +The UART interface is slow and needs a buffer for better synchronisation. Data is written in a FIFO. FIFO is the abrivation first in first out. This FIFO is realised in a ring buffer. Figure \ref{fig:FIFO pointer} explains how it works. Two pointers point at an address of internal RAM. The pointer nextwrite points to the address where the next incoming data will be written. When new data is incoming the FIFO the pointer is increased. Now valid data has to be read from the FIFO and the nextread is increased. If the two pointers in the FIFO are equal the FIFO is empty. + +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.5]{tx/BlockTX.png} + \caption{Blockdiagram TX} + \label{fig:Blockdiagram} + \end{center} +\end{figure} +\hrule +\lstinputlisting[style=vhdl]{tx/UART_TX_8N1.vhd} +\hrule +\vspace{10pt} +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.4]{tx/path6054.png} + \caption{FIFO pointer} + \label{fig:FIFO pointer} + \end{center} +\end{figure} + The FIFO is a circular buffer and works with two address pointers. One pointer is used to point at the write address. The other pointer points at the read address. Both pointers are increased with one step. The interface has two control signals for handshakes. send\_busy and send\_empty these are the FIFO states full and empty. The distance between nextwrite and nextread generates the signal busy because even one more wirte action would cause an overflow in the buffer. + The testbench is required. +\\ +\hrule +\lstinputlisting[style=vhdl]{tx/tb_UART_TX_8N1.vhd} +\hrule +\vspace{10pt} +Put both files in the same directory and simulate this testcase and check the timing requirements. + +\begin{verbatim} +ghdl -i *.vhd +ghdl -m tb_UART_TX_8N1 +ghdl -r tb_UART_TX_8N1 --stop-time=200us --wave=TX.ghw +gtkwave TX.ghw +\end{verbatim} + +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.3]{tx/TX_simple.png} + \caption{UART TX output} + \end{center} +\end{figure} + +\section{advanced RX Unit with FIFO} +The receiver is the opposite component of the transmitter. The code is mapped also in this article. The generic is used to set the right timing. The tick\_counter is the timer of one bit. The counter range of tick is calculated by the generic clk\_freq and baudrate. These parameters make the code portable into different designs. There is nothing to change inside the code when another frequency or baudrate are used. Such parameter makes source code simpiler reusable. When the transmission is off, the RX has a high on line. The state maschine is in idle and waits for RX to turn low. This condition is checked of the falling edge on the start bit. All other bits are cought in the middle of the bit time. +\\ +\hrule +\lstinputlisting[style=vhdl]{rx/UART_RX_8N1.vhd} +\hrule +\vspace{10pt} +Now the apposite testbench. +\hrule +\lstinputlisting[style=vhdl]{rx/tb_UART_RX_8N1.vhd} +\hrule +\vspace{10pt} + +\begin{verbatim} +ghdl -i *.vhd +ghdl -m tb_UART_RX_8N1 +ghdl -r tb_UART_RX_8N1 --stop-time=800us --wave=RX.ghw +gtkwave RX.ghw +\end{verbatim} + +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.3]{rx/sim_RX.png} + \caption{UART RX in} + \label{fig:sim RX} + \end{center} +\end{figure} + +\section{example application} +In the last sections we have designed an input and an output interface. By combinating the receiving and transmitting example, we can build the full UART. Now let us make a simple capitalisation ASCII engine. This is more a theoretical example for a demonstration. The data stream is very simple. It demonstrates how it works. +\\ +\hrule +\lstinputlisting[style=vhdl]{capitalisation/capitalisation.vhd} +\hrule +\vspace{10pt} + +The application has an 8bit input and a 8bit output interface. A top instance combine the application and the RX und TX interface together. RX and TX are the physical wires and board\_clk is the internal clock of all. This design is competent to fit inside an FPGA. +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.4]{capitalisation/zeichnung.png} + \end{center} +\end{figure} + +\hrule +\lstinputlisting[style=vhdl]{capitalisation/top_capitalisation.vhd} +\hrule +\vspace{10pt} +Also for this the testbench. +\\ +\hrule +\lstinputlisting[style=vhdl]{capitalisation/tb_capitalisation.vhd} +\hrule +\vspace{10pt} + +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.4]{capitalisation/capitalisation.png} + \caption{capitalisation} + \label{fig:capitalisation} + \end{center} +\end{figure} + +\section{Makefile for workflow} +Make is a build tool from the GNU Project. Mostly it is used to control compiling a huge number of files ans solve dependencies. For simplify your life and enhance your productivity you can use is also the make tool to prepair the target in the ghdl simulation. The makefile is like a script with sequential commands. Sometimes rules are insert. If you have larger designs, you should also divide the VHDL design into different files. I use \textbf{make} for this. Store the makefile into the same folder. For run in GHDL type make, this starts all commandos under all. And for view inside the timingdiagram type \textbf{make view}. You find many examples but I give you my makefile for a simple start in GHDL application. +\\ +\hrule +\VerbatimInput{capitalisation/makefile} +\hrule +\vspace{10pt} + + +\section{file in/out} +In former section we had simulate the whole desgin. In larger designs this can be difficult. It needs time to run and it can be also possible some parts are not read. You have to divide the design in moduls and you have to test the moduls by itselfs. Tested moduls can be integated inside the design. The simple 8bit interface is an good standard. Now I show you. How a module can be tested with datas from an file and also put the output into a file. Sometimes is this simpiler to check as a view in a timing diagram. +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.4]{file_in_out/zeichnung.png} + \end{center} +\end{figure} +The file \textbf{test.txt} is read and the characters goes into the capitalisation and are written in the file \textbf{text1.txt}. + +\vspace{10pt} +\\ +\hrule +\lstinputlisting[style=vhdl]{file_in_out/tb_file.vhd} +\hrule +\vspace{10pt} + +\begin{verbatim} +[test.txt] +Hallo world! Can you see my text? +\end{verbatim} + +\begin{verbatim} +[test1.txt] +HALLO WORLD! CAN YOU SEE MY TEXT? +\end{verbatim} +VHDL has only restricted file operations. It is not possible to seek the fileposition. + +\section{VHPI Interface to an other language} +Here I show one of the highest feature of GHDL. It is possible to link code from another language into the simulation. This can be used for a model or an interface to a real hardware. The possible speed is lower as in an FPGA. For testing is this a change to use mor realistic posibilities. You can data interchange of other programs, for instance testing software. In our case the simulation can communicate with a comport emulator. Linux has pseudoterminals witch is a serial interface in driver lowlever exchange of programs. +First start the c source file. There are only some c functions. +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.4]{vhpi/zeichnung.png} + \end{center} +\end{figure} +\vspace{10pt} +\\ +\hrule +\lstinputlisting[style=c]{vhpi/tty.c} +\hrule +\vspace{10pt} + +This package is the glue between external code. All c functions get a wrap of a vhdl definition. That makes possible to call a c function in vhdl. This is the advantage of this VHPI interface. +\vspace{10pt} +\hrule +\lstinputlisting[style=vhdl]{vhpi/tty_pkg.vhd} +\hrule +\vspace{10pt} +Also for that case the testbench. +\vspace{10pt} +\\ +\hrule +\lstinputlisting[style=vhdl]{vhpi/tb_tty.vhd} +\hrule +\vspace{10pt} +And the makefile that you can compile and link all together. +\hrule +\VerbatimInput{vhpi/makefile} +\hrule +\vspace{10pt} +In action the simulation prints out the name of the pseudotherminal. I can open a serial terminal program and send datas to the simulation and can also receive the output. + +\begin{figure}[H] + \begin{center} + \includegraphics[scale=0.5]{vhpi/terminal.png} + \end{center} +\end{figure} + +\section{closing words} + The chapter of testbench is very short in the most books. In this article you see the code for testing is adequate to code of application. A simulation is irrecoverable for good results. The development is only effective with simulation. Debug at a later development phase is very difficult. The testbench is the pusher for all effects. The code should also be reusable code. The generic is an interface to set some parameter for a simpler practical integration in the whole application. I hope you could follow all demonstrations and give you idea for better work. + + \begin{verbatim} + the procedure tx_char was posted of Lothar Miller on + http:\\www.mikrocontroller.net + + the VHPI interface for pseudotherminal was posted + of Wojciech M. Zabolotny on comp.arch.FPGA 2011 + \end{verbatim} + +\end{document} diff --git a/doc/using/UART_srcs/uart.toc b/doc/using/UART_srcs/uart.toc new file mode 100644 index 000000000..348a47af4 --- /dev/null +++ b/doc/using/UART_srcs/uart.toc @@ -0,0 +1,8 @@ +\contentsline {section}{\numberline {1}introduction UART transmission}{2}{section.1} +\contentsline {section}{\numberline {2}advanced TX Unit with FIFO}{2}{section.2} +\contentsline {section}{\numberline {3}advanced RX Unit with FIFO}{8}{section.3} +\contentsline {section}{\numberline {4}example application}{13}{section.4} +\contentsline {section}{\numberline {5}Makefile for workflow}{19}{section.5} +\contentsline {section}{\numberline {6}file in/out}{19}{section.6} +\contentsline {section}{\numberline {7}VHPI Interface to an other language}{22}{section.7} +\contentsline {section}{\numberline {8}closing words}{28}{section.8} diff --git a/doc/using/UART_srcs/vhpi/Zeichnung.svg b/doc/using/UART_srcs/vhpi/Zeichnung.svg new file mode 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--work=work --workdir=work tb_tty.vhd + + ghdl -e -Wl,tty.o --ieee=synopsys -fexplicit --workdir=work -Pwork tb_tty +# ghdl -r tb_tty --wave=tbench.ghw + ghdl -r tb_tty --wave=tbench.ghw --stop-time=500000us + + +view: + gtkwave tbench.ghw a.gtkw + diff --git a/doc/using/UART_srcs/vhpi/tb_tty.vhd b/doc/using/UART_srcs/vhpi/tb_tty.vhd new file mode 100644 index 000000000..6e1576ed5 --- /dev/null +++ b/doc/using/UART_srcs/vhpi/tb_tty.vhd @@ -0,0 +1,116 @@ +--tb_tty.vhd +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +use work.tty_pkg.all; + +ENTITY tb_tty IS +END tb_tty; + +ARCHITECTURE behavior OF tb_tty IS + +signal clk : std_logic := '0'; +signal reset : std_logic; + +signal data_in : std_logic_vector(7 downto 0); +signal wdata : std_logic_vector(7 downto 0); +signal wr_en : std_logic:='1'; +signal wr : std_logic; +signal rd_en : std_logic; +signal rd : std_logic; +signal a : integer; +signal c : integer; + + +component capitalisation is + port( + clk : in std_logic; + reset : in std_logic; + --in + rdata : in std_logic_vector(7 downto 0); + rd_en : in std_logic; + rd : out std_logic; + --out + wdata : out std_logic_vector(7 downto 0); + wr_en : in std_logic; + wr : out std_logic + ); +end component; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +subtype by_te is character; +type f_byte is file of by_te; + +BEGIN + +--file open + process + begin c<=tty_open(0); + wait; + end process; + +--read +process (clk) + +variable b: integer; +begin + if rising_edge(CLK) then + a<= read_enable(0); + if a=1 then + data_in<=std_logic_vector(to_unsigned(read_data(0),8)); + rd_en<='1'; + else + rd_en<='0'; + end if; + end if; + +end process; + +--write +process (clk) +variable b: integer; + + begin + if rising_edge(CLK) then + if reset='0' then + if wr='1' then + b:=to_integer(unsigned(wdata)); + write_data(b); + end if; + end if; + end if; + end process; + + stim_proc : process + begin + reset <= '1'; + + wait for 50 ns; + reset <='0'; + wait; + end process; + + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + +engine: capitalisation + port map( + clk => clk, + reset => reset, + --in + rdata => data_in, + rd_en => rd_en, + rd => rd, + --out + wdata => wdata, + wr_en => wr_en, + wr => wr + ); +END; diff --git a/doc/using/UART_srcs/vhpi/terminal.png b/doc/using/UART_srcs/vhpi/terminal.png Binary files differnew file mode 100644 index 000000000..a19f3cd64 --- /dev/null +++ b/doc/using/UART_srcs/vhpi/terminal.png diff --git a/doc/using/UART_srcs/vhpi/tty.c b/doc/using/UART_srcs/vhpi/tty.c new file mode 100644 index 000000000..c04f8f359 --- /dev/null +++ b/doc/using/UART_srcs/vhpi/tty.c @@ -0,0 +1,83 @@ +/* + VPI code allowing you to connect terminal emulator or other program to pty "connected" + to the UART-like port in IP core simulated in GHDL. + + This code is written by Wojciech M. Zabolotny (wz...@ise.pw.edu.pl) on 2nd June 2011 + and is published as PUBLIC DOMAIN + +*/ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <stdarg.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/ioctl.h> +#include <linux/ioctl.h> +#include <sys/stat.h> +#include <sys/poll.h> +#include <fcntl.h> +#include <errno.h> + +char *ptsname(int fd); + +int ptyf = -1; + + + +int tty_open(int a) +{ + ptyf = open("/dev/ptmx",O_RDWR); + if(ptyf<0) { + perror("I can't open pseudoterminal\n"); + return -1; + } + if(unlockpt(ptyf)<0) { + perror("I can't unlock pseudoterminal\n"); + return -1; + } + if(grantpt(ptyf)<0) { + perror("I can't grant pseudoterminal\n"); + return -1; + } + printf("Pseudoterminal: %s\n",ptsname(ptyf)); + // sleep(10); + return 0; +} + + +int read_enable(void) +{ + //In the masks below you may omit POLLHUP in this case + //disconnection of the terminal emulator from pty will not + //stop simulation, and you'll be able to reconnect + //the same or different program to pty and running simulation + struct pollfd pfd[1]={{ptyf,POLLIN | POLLERR | POLLHUP,0}}; + int res; + res=poll(pfd,1,0); + if(res==0) return 0; + if(res<0) return 0; //error + //If you removed POLLHUP from the mask above, you should remove it below too + if(pfd[0].revents & (POLLERR|POLLHUP)) return 0; //disconnected or error? + if(pfd[0].revents & POLLIN) return 1; + return 0; +} + + +int read_data(void) +{ + unsigned char c; + read(ptyf,&c,1); + return c; +} + +int write_data(int byte) +{ + unsigned char c = byte; + write(ptyf,&c,1); + + // Debug: printf("Writing %x to pty\n", c); + return 0; +} + diff --git a/doc/using/UART_srcs/vhpi/tty_pkg.vhd b/doc/using/UART_srcs/vhpi/tty_pkg.vhd new file mode 100644 index 000000000..99e3a347f --- /dev/null +++ b/doc/using/UART_srcs/vhpi/tty_pkg.vhd @@ -0,0 +1,70 @@ +--tty_pkg.vhd +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package tty_pkg is + + function to_integer( s: std_logic) return integer; + function to_std_logic( s : integer ) return std_logic; + + function tty_open (portn : integer) return integer; + attribute foreign of tty_open : + function is "VHPIDIRECT tty_open"; + + function read_data ( dummy: integer) return integer; + attribute foreign of read_data : + function is "VHPIDIRECT read_data"; + + function read_enable ( dummy: integer) return integer; + attribute foreign of read_enable : + function is "VHPIDIRECT read_enable"; + + procedure write_data ( data: in integer); + attribute foreign of write_data : + procedure is "VHPIDIRECT write_data"; + +end; + + +package body tty_pkg is + + function to_integer( s : std_logic ) return integer is + begin + if s = '1' then + return 1; + else + return 0; + end if; + end function; + + function to_std_logic( s : integer ) return std_logic is + begin + if s > 0 then + return '1'; + else + return '0'; + end if; + end function; + + + function tty_open (portn : integer) return integer is + begin + assert false report "VHPI" severity failure; + end tty_open; + + function read_data (dummy: integer) return integer is + begin + assert false report "VHPI" severity failure; + end read_data; + + function read_enable (dummy: integer) return integer is + begin + assert false report "VHPI" severity failure; + end read_enable; + + procedure write_data ( data: in integer) is + begin + assert false report "VHPI" severity failure; + end write_data; +end tty_pkg; diff --git a/doc/using/UART_srcs/vhpi/zeichnung.png b/doc/using/UART_srcs/vhpi/zeichnung.png Binary files differnew file mode 100644 index 000000000..fbfdec259 --- /dev/null +++ b/doc/using/UART_srcs/vhpi/zeichnung.png |
