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Diffstat (limited to 'doc/using/Synthesis.rst')
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1 files changed, 37 insertions, 34 deletions
diff --git a/doc/using/Synthesis.rst b/doc/using/Synthesis.rst index f7dac2abf..fccfad9c6 100644 --- a/doc/using/Synthesis.rst +++ b/doc/using/Synthesis.rst @@ -5,7 +5,8 @@ Synthesis ######### .. WARNING:: - This is experimental and work in progress! If you find crashes or unsupported features, please :ref:`report them <reporting_bugs>`! + This is experimental and work in progress! If you find crashes or unsupported features, please + :ref:`report them <reporting_bugs>`! Since ``v0.37``, GHDL features a built-in (experimental) synthesis kernel with two backends: ``synth`` and ``yosys-plugin``. Currently, synthesis is supported as a front-end of other synthesis and technology mapping tools. @@ -18,29 +19,27 @@ Hence, the netlists generated by GHDL are not optimised. Synthesis [``--synth``] *********************** -.. HINT:: - This command is useful for checking that a design can be synthesized, before actually running a complete synthesis - tool. In fact, because this is expected to be much faster, it can be used as a frequent check. +This command is useful for checking that a design can be synthesized, before actually running a complete synthesis +tool. In fact, because this is expected to be much faster, it can be used as a frequent check. -.. TIP:: - Since GHDL's front-end supports multiple versions of the standard, but the synthesised netlists are generated using - a subset of VHDL 1993, GHDL's synthesis features can be used as a preprocessor with tools that do support older - versions of the standard, but which don't provide the most recent features. +Moreover, since GHDL's front-end supports multiple versions of the standard, but the synthesised netlists are generated +using a subset of VHDL 1993, GHDL's synthesis features can be used as a preprocessor with tools that do support older +versions of the standard, but which don't provide the most recent features. + +Currently, the default output is a generic netlist using a (very simple) subset of VHDL 1993. +See :option:`--out` and :ghdlsharp:`1174` for on-going discussion about other output formats. -.. option:: --synth <[options] primary_unit [secondary_unit]> +.. option:: --synth <[options] [library.]top_unit [arch]> -Elaborates for synthesis the design whose top unit is indicated by ``primary_unit [secondary_unit]``. +Elaborates for synthesis the design whose top unit is indicated by ``[library.]top_unit [arch]``. .. ATTENTION:: All the units must have been analyzed; that is, the artifacts of previously executed :option:`-a` calls must exist. -.. option:: --synth <[options] files... -e primary_unit [secondary_unit]> +.. option:: --synth <[options] files... -e top_unit [arch]> Analyses and elaborates for synthesis the files present on the command line only. -Elaboration starts from the top unit indicated by ``primary_unit [secondary_unit]``. - -Currently, the default output is a generic netlist using a (very simple) subset of VHDL 1993. -See :option:`--out` and :ghdlsharp:`1174` for on-going discussion about other output formats. +Elaboration starts from the top unit indicated by ``top_unit [arch]``. .. TIP:: Files can be provided in any order. @@ -61,30 +60,34 @@ Synthesis options * ``-- synthesis translate_on`` * ``-- synopsys synthesis_off`` -Due to GHDL's modular architecture (see :ref:`INT:Overview`), the synthesis kernel shares the VHDL parsing front-end with the -simulation back-ends. Hence, available options for synthesis are the same as for analysis and/or simulation elaboration -(see :ref:`GHDL:options`). In addition to those options, there are some synthesis specific options. +Due to GHDL's modular architecture (see :ref:`INT:Overview`), the synthesis kernel shares the VHDL parsing front-end +with the simulation back-ends. +Hence, available options for synthesis are the same as for analysis and/or simulation elaboration +(see :ref:`GHDL:options`). +In addition to those options, there are some synthesis specific options. .. TIP:: - Furthermore there are lot of debug options available. Beware: these debug options should only used - for debugging purposes as they aren't guaranteed to be stable during development of GHDL's synthesis feature. + Furthermore there are lot of debug options available. + Beware: these debug options should only used for debugging purposes as they aren't guaranteed to be stable during + development of GHDL's synthesis feature. You can find them in the file :ghdlsrc:`ghdlsynth.adb <ghdldrv/ghdlsynth.adb>` in the procedure ``Decode_Option()``. .. option:: -gNAME=VALUE - Override top unit generic `NAME` with value `VALUE`. Similar to the run-time option :option:`-gGENERIC`. + Override top unit generic `NAME` with value `VALUE`. + Similar to the run-time option :option:`-gGENERIC`. Example:: - $ ghdl --synth --std=08 -gDEPTH=12 my_unit + $ ghdl --synth --std=08 -gDEPTH=12 [library.]top_unit [arch] .. option:: --out=<vhdl|raw-vhdl|dot|none|raw|dump> * **vhdl** *(default)*: equivalent to ``raw-vhdl``, but the original top-level unit is preserved unmodified, so the synthesized design can be simulated with the same testbench. - * **raw-vhdl**: all statements are converted to a simple VHDL 1993 netlist, for allowing instantiation in other synthesis - tools without modern VHDL support. + * **raw-vhdl**: all statements are converted to a simple VHDL 1993 netlist, for allowing instantiation in other + synthesis tools without modern VHDL support. * **dot**: generate a graphviz dot diagram of the netlist AST. @@ -100,7 +103,7 @@ simulation back-ends. Hence, available options for synthesis are the same as for Example:: - $ ghdl --synth --std=08 --vendor-library=vendorlib my_unit + $ ghdl --synth --std=08 --vendor-library=vendorlib [library.]top_unit [arch] Assertions, PSL and formal verification ======================================= @@ -111,7 +114,7 @@ Assertions, PSL and formal verification Example:: - $ ghdl --synth --std=08 --no-formal my_unit + $ ghdl --synth --std=08 --no-formal [library.]top_unit [arch] .. option:: --no-assert-cover @@ -120,7 +123,7 @@ Assertions, PSL and formal verification Example:: - $ ghdl --synth --std=08 --no-assert-cover my_unit + $ ghdl --synth --std=08 --no-assert-cover [library.]top_unit [arch] .. option:: --assert-assumes @@ -130,7 +133,7 @@ Assertions, PSL and formal verification Example:: - $ ghdl --synth --std=08 --assert-assumes my_unit + $ ghdl --synth --std=08 --assert-assumes [library.]top_unit [arch] As all PSL asserts are treated like PSL assumes, no `cover` directives are automatically generated for them, regardless of using the :option:`--no-assert-cover` or not. @@ -144,7 +147,7 @@ Assertions, PSL and formal verification Example:: - $ ghdl --synth --std=08 --assume-asserts my_unit + $ ghdl --synth --std=08 --assume-asserts [library.]top_unit [arch] `cover` directives are automatically generated for the resulting asserts (with an implication operator) if :option:`--no-assert-cover` isn't used. @@ -183,35 +186,35 @@ To Verilog .. code-block:: shell - yosys -m ghdl -p 'ghdl filename.vhdl -e unit_name; write_verilog filename.v' + yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_verilog filename.v' To EDIF ------- .. code-block:: shell - yosys -m ghdl -p 'ghdl filename.vhdl -e unit_name; write_edif filename.edif' + yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_edif filename.edif' To SMT ------ .. code-block:: shell - yosys -m ghdl -p 'ghdl filename.vhdl -e unit_name; write_smt2 filename.smt2' + yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_smt2 filename.smt2' To BTOR2 -------- .. code-block:: shell - yosys -m ghdl -p 'ghdl filename.vhdl -e unit_name; write_btor filename.btor' + yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_btor filename.btor' To FIRRTL --------- .. code-block:: shell - yosys -m ghdl -p 'ghdl filename.vhdl -e unit_name; write_firrtl filename.firrtl' + yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_firrtl filename.firrtl' To VHDL ------- |