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-rw-r--r--testsuite/synth/issue1209/issue.vhdl22
-rwxr-xr-xtestsuite/synth/issue1209/testsuite.sh9
2 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/synth/issue1209/issue.vhdl b/testsuite/synth/issue1209/issue.vhdl
new file mode 100644
index 000000000..6402eb4a3
--- /dev/null
+++ b/testsuite/synth/issue1209/issue.vhdl
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+
+entity issue is
+ generic(
+ data_width : integer := 4
+ );
+ port(
+ clk : in std_logic;
+ di : in std_logic_vector(data_width - 1 downto 0);
+ do : out std_logic_vector(data_width - 1 downto 0)
+ );
+end issue;
+
+architecture behavioral of issue is
+ constant base_const : std_logic_vector(data_width - 1 downto 0) := conv_std_logic_vector(3, data_width);
+ constant new_const : std_logic_vector(data_width - 1 downto 0) := base_const + "0100";
+begin
+ do <= new_const;
+end behavioral;
diff --git a/testsuite/synth/issue1209/testsuite.sh b/testsuite/synth/issue1209/testsuite.sh
new file mode 100755
index 000000000..ea40a1eb4
--- /dev/null
+++ b/testsuite/synth/issue1209/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=-fsynopsys
+synth_analyze issue
+clean
+
+echo "Test successful"