diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 75 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/tokens.py | 42 | ||||
| -rw-r--r-- | src/ghdldrv/ghdlprint.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-canon.adb | 40 | ||||
| -rw-r--r-- | src/vhdl/vhdl-elocations.adb | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-elocations.ads | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-errors.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.adb | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 33 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes_meta.adb | 210 | ||||
| -rw-r--r-- | src/vhdl/vhdl-parse.adb | 28 | ||||
| -rw-r--r-- | src/vhdl/vhdl-prints.adb | 19 | ||||
| -rw-r--r-- | src/vhdl/vhdl-scanner.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 15 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.ads | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_stmts.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-tokens.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-tokens.ads | 2 |
20 files changed, 357 insertions, 130 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 62aac4a98..90e0339cf 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -132,6 +132,7 @@ class Iir_Kind: Interface_Package_Declaration = 117 Interface_Function_Declaration = 118 Interface_Procedure_Declaration = 119 +<<<<<<< HEAD Anonymous_Signal_Declaration = 120 Signal_Attribute_Declaration = 121 Identity_Operator = 122 @@ -200,6 +201,76 @@ class Iir_Kind: Concurrent_Procedure_Call_Statement = 185 Psl_Assert_Statement = 186 Psl_Cover_Statement = 187 +======= + Signal_Attribute_Declaration = 120 + Identity_Operator = 121 + Negation_Operator = 122 + Absolute_Operator = 123 + Not_Operator = 124 + Implicit_Condition_Operator = 125 + Condition_Operator = 126 + Reduction_And_Operator = 127 + Reduction_Or_Operator = 128 + Reduction_Nand_Operator = 129 + Reduction_Nor_Operator = 130 + Reduction_Xor_Operator = 131 + Reduction_Xnor_Operator = 132 + And_Operator = 133 + Or_Operator = 134 + Nand_Operator = 135 + Nor_Operator = 136 + Xor_Operator = 137 + Xnor_Operator = 138 + Equality_Operator = 139 + Inequality_Operator = 140 + Less_Than_Operator = 141 + Less_Than_Or_Equal_Operator = 142 + Greater_Than_Operator = 143 + Greater_Than_Or_Equal_Operator = 144 + Match_Equality_Operator = 145 + Match_Inequality_Operator = 146 + Match_Less_Than_Operator = 147 + Match_Less_Than_Or_Equal_Operator = 148 + Match_Greater_Than_Operator = 149 + Match_Greater_Than_Or_Equal_Operator = 150 + Sll_Operator = 151 + Sla_Operator = 152 + Srl_Operator = 153 + Sra_Operator = 154 + Rol_Operator = 155 + Ror_Operator = 156 + Addition_Operator = 157 + Substraction_Operator = 158 + Concatenation_Operator = 159 + Multiplication_Operator = 160 + Division_Operator = 161 + Modulus_Operator = 162 + Remainder_Operator = 163 + Exponentiation_Operator = 164 + Function_Call = 165 + Aggregate = 166 + Parenthesis_Expression = 167 + Qualified_Expression = 168 + Type_Conversion = 169 + Allocator_By_Expression = 170 + Allocator_By_Subtype = 171 + Selected_Element = 172 + Dereference = 173 + Implicit_Dereference = 174 + Slice_Name = 175 + Indexed_Name = 176 + Psl_Expression = 177 + Sensitized_Process_Statement = 178 + Process_Statement = 179 + Concurrent_Simple_Signal_Assignment = 180 + Concurrent_Conditional_Signal_Assignment = 181 + Concurrent_Selected_Signal_Assignment = 182 + Concurrent_Assertion_Statement = 183 + Concurrent_Procedure_Call_Statement = 184 + Psl_Assert_Statement = 185 + Psl_Cover_Statement = 186 + Psl_Restrict_Directive = 187 +>>>>>>> vhdl: parse and analyze restrict directive. Block_Statement = 188 If_Generate_Statement = 189 Case_Generate_Statement = 190 @@ -457,7 +528,8 @@ class Iir_Kinds: Iir_Kind.Concurrent_Assertion_Statement, Iir_Kind.Concurrent_Procedure_Call_Statement, Iir_Kind.Psl_Assert_Statement, - Iir_Kind.Psl_Cover_Statement] + Iir_Kind.Psl_Cover_Statement, + Iir_Kind.Psl_Restrict_Directive] Non_Alias_Object_Declaration = [ Iir_Kind.File_Declaration, @@ -649,6 +721,7 @@ class Iir_Kinds: Iir_Kind.Concurrent_Procedure_Call_Statement, Iir_Kind.Psl_Assert_Statement, Iir_Kind.Psl_Cover_Statement, + Iir_Kind.Psl_Restrict_Directive, Iir_Kind.Block_Statement, Iir_Kind.If_Generate_Statement, Iir_Kind.Case_Generate_Statement, diff --git a/python/libghdl/thin/vhdl/tokens.py b/python/libghdl/thin/vhdl/tokens.py index 572c3906d..20cf3b7dd 100644 --- a/python/libghdl/thin/vhdl/tokens.py +++ b/python/libghdl/thin/vhdl/tokens.py @@ -181,23 +181,25 @@ class Tok: Psl_Sequence = 177 Psl_Endpoint = 178 Psl_Cover = 179 - Psl_Const = 180 - Psl_Boolean = 181 - Inf = 182 - Within = 183 - Abort = 184 - Before = 185 - Before_Em = 186 - Before_Un = 187 - Before_Em_Un = 188 - Until_Em = 189 - Until_Un = 190 - Until_Em_Un = 191 - Always = 192 - Never = 193 - Eventually = 194 - Next_A = 195 - Next_E = 196 - Next_Event = 197 - Next_Event_A = 198 - Next_Event_E = 199 + Psl_Restrict = 180 + Psl_Restrict_Guarantee = 181 + Psl_Const = 182 + Psl_Boolean = 183 + Inf = 184 + Within = 185 + Abort = 186 + Before = 187 + Before_Em = 188 + Before_Un = 189 + Before_Em_Un = 190 + Until_Em = 191 + Until_Un = 192 + Until_Em_Un = 193 + Always = 194 + Never = 195 + Eventually = 196 + Next_A = 197 + Next_E = 198 + Next_Event = 199 + Next_Event_A = 200 + Next_Event_E = 201 diff --git a/src/ghdldrv/ghdlprint.adb b/src/ghdldrv/ghdlprint.adb index 8cd8de53f..6c5cd5873 100644 --- a/src/ghdldrv/ghdlprint.adb +++ b/src/ghdldrv/ghdlprint.adb @@ -396,6 +396,8 @@ package body Ghdlprint is | Tok_Psl_Sequence | Tok_Psl_Endpoint | Tok_Psl_Cover + | Tok_Psl_Restrict + | Tok_Psl_Restrict_Guarantee | Tok_Psl_Boolean | Tok_Psl_Const | Tok_Inf diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 3f20085b4..85d6b664f 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1107,6 +1107,8 @@ package body Synth.Stmts is when Iir_Kind_Component_Instantiation_Statement => -- TODO. null; + when Iir_Kind_Psl_Default_Clock => + null; when others => Error_Kind ("synth_statements", Stmt); end case; diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 0dfe1a67a..c6415c229 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1043,7 +1043,8 @@ package body Vhdl.Annotations is null; when Iir_Kind_Psl_Cover_Statement - | Iir_Kind_Psl_Assert_Statement => + | Iir_Kind_Psl_Assert_Statement + | Iir_Kind_Psl_Restrict_Directive => null; when Iir_Kind_Psl_Endpoint_Declaration => Create_Object_Info (Block_Info, El, Kind_PSL); diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 5e1011a36..8c8922fce 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -1763,6 +1763,25 @@ package body Vhdl.Canon is Set_PSL_Clock_Sensitivity (Stmt, List); end Canon_Psl_Clocked_NFA; + procedure Canon_Psl_Sequence_Directive (Stmt : Iir) + is + Seq : PSL_Node; + Fa : PSL_NFA; + begin + Seq := Get_Psl_Sequence (Stmt); + Seq := PSL.Rewrites.Rewrite_SERE (Seq); + Set_Psl_Sequence (Stmt, Seq); + + -- Generate the NFA. + Fa := PSL.Build.Build_SERE_FA (Seq); + Set_PSL_NFA (Stmt, Fa); + + Canon_Psl_Clocked_NFA (Stmt); + if Canon_Flag_Expressions then + Canon_PSL_Expression (Get_PSL_Clock (Stmt)); + end if; + end Canon_Psl_Sequence_Directive; + procedure Canon_Psl_Directive (Stmt : Iir) is begin Canon_Psl_Clocked_NFA (Stmt); @@ -2123,20 +2142,13 @@ package body Vhdl.Canon is end; when Iir_Kind_Psl_Cover_Statement => - declare - Seq : PSL_Node; - Fa : PSL_NFA; - begin - Seq := Get_Psl_Sequence (El); - Seq := PSL.Rewrites.Rewrite_SERE (Seq); - Set_Psl_Sequence (El, Seq); - - -- Generate the NFA. - Fa := PSL.Build.Build_SERE_FA (Seq); - Set_PSL_NFA (El, Fa); - - Canon_Psl_Directive (El); - end; + Canon_Psl_Sequence_Directive (El); + if Canon_Flag_Expressions then + Canon_Expression (Get_Severity_Expression (El)); + Canon_Expression (Get_Report_Expression (El)); + end if; + when Iir_Kind_Psl_Restrict_Directive => + Canon_Psl_Sequence_Directive (El); when Iir_Kind_Psl_Default_Clock => null; diff --git a/src/vhdl/vhdl-elocations.adb b/src/vhdl/vhdl-elocations.adb index c08519076..78a97605c 100644 --- a/src/vhdl/vhdl-elocations.adb +++ b/src/vhdl/vhdl-elocations.adb @@ -344,6 +344,7 @@ package body Vhdl.Elocations is | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Case_Generate_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Simple_Simultaneous_Statement diff --git a/src/vhdl/vhdl-elocations.ads b/src/vhdl/vhdl-elocations.ads index 643746527..c104247c1 100644 --- a/src/vhdl/vhdl-elocations.ads +++ b/src/vhdl/vhdl-elocations.ads @@ -406,6 +406,7 @@ package Vhdl.Elocations is -- Iir_Kind_Psl_Assert_Statement (None) -- Iir_Kind_Psl_Cover_Statement (None) + -- Iir_Kind_Psl_Restrict_Directive (None) -- Iir_Kind_Component_Instantiation_Statement (L3) -- diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb index db2f87601..e4c7ba93c 100644 --- a/src/vhdl/vhdl-errors.adb +++ b/src/vhdl/vhdl-errors.adb @@ -691,6 +691,8 @@ package body Vhdl.Errors is return Disp_Label (Node, "PSL assertion"); when Iir_Kind_Psl_Cover_Statement => return Disp_Label (Node, "PSL cover"); + when Iir_Kind_Psl_Restrict_Directive => + return "PSL restrict"; when Iir_Kind_Psl_Default_Clock => return "PSL default clock"; diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index ae1c2bcb0..70c62b692 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1237,6 +1237,7 @@ package body Vhdl.Nodes is | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Simple_Simultaneous_Statement diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 26d9601f8..5d8c902b1 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -2923,6 +2923,34 @@ package Vhdl.Nodes is -- -- Get/Set_Visible_Flag (Flag4) + -- Iir_Kind_Psl_Restrict_Directive (Medium) + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Psl_Sequence (Field1) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Label (Field3) + -- Get/Set_Identifier (Alias Field3) + -- + -- The following fields are set by canon. + -- Get/Set_PSL_Clock (Field7) + -- + -- Get/Set_PSL_NFA (Field8) + -- + -- Number of states in the NFA. + -- Get/Set_PSL_Nbr_States (Field9) + -- + -- Get/Set_PSL_Clock_Sensitivity (Field10) + -- + -- True if at least one of the NFA edge has the EOS flag. + -- Get/Set_PSL_EOS_Flag (Flag1) + -- + -- Get/Set_Postponed_Flag (Flag3) + -- + -- Get/Set_Visible_Flag (Flag4) + -- Iir_Kind_Component_Instantiation_Statement (Medium) -- -- LRM08 11.7 Component instantiation statements @@ -4334,6 +4362,7 @@ package Vhdl.Nodes is Iir_Kind_Concurrent_Procedure_Call_Statement, Iir_Kind_Psl_Assert_Statement, Iir_Kind_Psl_Cover_Statement, + Iir_Kind_Psl_Restrict_Directive, Iir_Kind_Block_Statement, Iir_Kind_If_Generate_Statement, Iir_Kind_Case_Generate_Statement, @@ -5506,6 +5535,7 @@ package Vhdl.Nodes is --Iir_Kind_Concurrent_Procedure_Call_Statement --Iir_Kind_Psl_Assert_Statement --Iir_Kind_Psl_Cover_Statement + --Iir_Kind_Psl_Restrict_Directive --Iir_Kind_Block_Statement --Iir_Kind_If_Generate_Statement --Iir_Kind_Case_Generate_Statement @@ -5522,7 +5552,8 @@ package Vhdl.Nodes is --Iir_Kind_Concurrent_Assertion_Statement --Iir_Kind_Concurrent_Procedure_Call_Statement --Iir_Kind_Psl_Assert_Statement - Iir_Kind_Psl_Cover_Statement; + --Iir_Kind_Psl_Cover_Statement + Iir_Kind_Psl_Restrict_Directive; subtype Iir_Kinds_Concurrent_Signal_Assignment is Iir_Kind range Iir_Kind_Concurrent_Simple_Signal_Assignment .. diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index eea011a3f..712d0fa81 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -1392,6 +1392,8 @@ package body Vhdl.Nodes_Meta is return "psl_assert_statement"; when Iir_Kind_Psl_Cover_Statement => return "psl_cover_statement"; + when Iir_Kind_Psl_Restrict_Directive => + return "psl_restrict_directive"; when Iir_Kind_Block_Statement => return "block_statement"; when Iir_Kind_If_Generate_Statement => @@ -3821,6 +3823,18 @@ package body Vhdl.Nodes_Meta is Field_Severity_Expression, Field_Report_Expression, Field_PSL_Clock_Sensitivity, + -- Iir_Kind_Psl_Restrict_Directive + Field_Psl_Sequence, + Field_Label, + Field_PSL_Clock, + Field_PSL_NFA, + Field_PSL_Nbr_States, + Field_PSL_EOS_Flag, + Field_Postponed_Flag, + Field_Visible_Flag, + Field_Parent, + Field_Chain, + Field_PSL_Clock_Sensitivity, -- Iir_Kind_Block_Statement Field_Label, Field_Visible_Flag, @@ -4628,88 +4642,89 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Concurrent_Procedure_Call_Statement => 1385, Iir_Kind_Psl_Assert_Statement => 1398, Iir_Kind_Psl_Cover_Statement => 1411, - Iir_Kind_Block_Statement => 1425, - Iir_Kind_If_Generate_Statement => 1436, - Iir_Kind_Case_Generate_Statement => 1445, - Iir_Kind_For_Generate_Statement => 1454, - Iir_Kind_Component_Instantiation_Statement => 1465, - Iir_Kind_Psl_Default_Clock => 1469, - Iir_Kind_Simple_Simultaneous_Statement => 1476, - Iir_Kind_Generate_Statement_Body => 1487, - Iir_Kind_If_Generate_Else_Clause => 1493, - Iir_Kind_Simple_Signal_Assignment_Statement => 1503, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1513, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1524, - Iir_Kind_Null_Statement => 1528, - Iir_Kind_Assertion_Statement => 1535, - Iir_Kind_Report_Statement => 1541, - Iir_Kind_Wait_Statement => 1549, - Iir_Kind_Variable_Assignment_Statement => 1556, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1563, - Iir_Kind_Return_Statement => 1569, - Iir_Kind_For_Loop_Statement => 1578, - Iir_Kind_While_Loop_Statement => 1587, - Iir_Kind_Next_Statement => 1594, - Iir_Kind_Exit_Statement => 1601, - Iir_Kind_Case_Statement => 1609, - Iir_Kind_Procedure_Call_Statement => 1615, - Iir_Kind_If_Statement => 1625, - Iir_Kind_Elsif => 1631, - Iir_Kind_Character_Literal => 1639, - Iir_Kind_Simple_Name => 1647, - Iir_Kind_Selected_Name => 1656, - Iir_Kind_Operator_Symbol => 1662, - Iir_Kind_Reference_Name => 1666, - Iir_Kind_External_Constant_Name => 1674, - Iir_Kind_External_Signal_Name => 1682, - Iir_Kind_External_Variable_Name => 1691, - Iir_Kind_Selected_By_All_Name => 1697, - Iir_Kind_Parenthesis_Name => 1702, - Iir_Kind_Package_Pathname => 1706, - Iir_Kind_Absolute_Pathname => 1707, - Iir_Kind_Relative_Pathname => 1708, - Iir_Kind_Pathname_Element => 1713, - Iir_Kind_Base_Attribute => 1715, - Iir_Kind_Subtype_Attribute => 1720, - Iir_Kind_Element_Attribute => 1725, - Iir_Kind_Left_Type_Attribute => 1730, - Iir_Kind_Right_Type_Attribute => 1735, - Iir_Kind_High_Type_Attribute => 1740, - Iir_Kind_Low_Type_Attribute => 1745, - Iir_Kind_Ascending_Type_Attribute => 1750, - Iir_Kind_Image_Attribute => 1756, - Iir_Kind_Value_Attribute => 1762, - Iir_Kind_Pos_Attribute => 1768, - Iir_Kind_Val_Attribute => 1774, - Iir_Kind_Succ_Attribute => 1780, - Iir_Kind_Pred_Attribute => 1786, - Iir_Kind_Leftof_Attribute => 1792, - Iir_Kind_Rightof_Attribute => 1798, - Iir_Kind_Delayed_Attribute => 1807, - Iir_Kind_Stable_Attribute => 1816, - Iir_Kind_Quiet_Attribute => 1825, - Iir_Kind_Transaction_Attribute => 1834, - Iir_Kind_Event_Attribute => 1838, - Iir_Kind_Active_Attribute => 1842, - Iir_Kind_Last_Event_Attribute => 1846, - Iir_Kind_Last_Active_Attribute => 1850, - Iir_Kind_Last_Value_Attribute => 1854, - Iir_Kind_Driving_Attribute => 1858, - Iir_Kind_Driving_Value_Attribute => 1862, - Iir_Kind_Behavior_Attribute => 1862, - Iir_Kind_Structure_Attribute => 1862, - Iir_Kind_Simple_Name_Attribute => 1869, - Iir_Kind_Instance_Name_Attribute => 1874, - Iir_Kind_Path_Name_Attribute => 1879, - Iir_Kind_Left_Array_Attribute => 1886, - Iir_Kind_Right_Array_Attribute => 1893, - Iir_Kind_High_Array_Attribute => 1900, - Iir_Kind_Low_Array_Attribute => 1907, - Iir_Kind_Length_Array_Attribute => 1914, - Iir_Kind_Ascending_Array_Attribute => 1921, - Iir_Kind_Range_Array_Attribute => 1928, - Iir_Kind_Reverse_Range_Array_Attribute => 1935, - Iir_Kind_Attribute_Name => 1944 + Iir_Kind_Psl_Restrict_Directive => 1422, + Iir_Kind_Block_Statement => 1436, + Iir_Kind_If_Generate_Statement => 1447, + Iir_Kind_Case_Generate_Statement => 1456, + Iir_Kind_For_Generate_Statement => 1465, + Iir_Kind_Component_Instantiation_Statement => 1476, + Iir_Kind_Psl_Default_Clock => 1480, + Iir_Kind_Simple_Simultaneous_Statement => 1487, + Iir_Kind_Generate_Statement_Body => 1498, + Iir_Kind_If_Generate_Else_Clause => 1504, + Iir_Kind_Simple_Signal_Assignment_Statement => 1514, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1524, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1535, + Iir_Kind_Null_Statement => 1539, + Iir_Kind_Assertion_Statement => 1546, + Iir_Kind_Report_Statement => 1552, + Iir_Kind_Wait_Statement => 1560, + Iir_Kind_Variable_Assignment_Statement => 1567, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1574, + Iir_Kind_Return_Statement => 1580, + Iir_Kind_For_Loop_Statement => 1589, + Iir_Kind_While_Loop_Statement => 1598, + Iir_Kind_Next_Statement => 1605, + Iir_Kind_Exit_Statement => 1612, + Iir_Kind_Case_Statement => 1620, + Iir_Kind_Procedure_Call_Statement => 1626, + Iir_Kind_If_Statement => 1636, + Iir_Kind_Elsif => 1642, + Iir_Kind_Character_Literal => 1650, + Iir_Kind_Simple_Name => 1658, + Iir_Kind_Selected_Name => 1667, + Iir_Kind_Operator_Symbol => 1673, + Iir_Kind_Reference_Name => 1677, + Iir_Kind_External_Constant_Name => 1685, + Iir_Kind_External_Signal_Name => 1693, + Iir_Kind_External_Variable_Name => 1702, + Iir_Kind_Selected_By_All_Name => 1708, + Iir_Kind_Parenthesis_Name => 1713, + Iir_Kind_Package_Pathname => 1717, + Iir_Kind_Absolute_Pathname => 1718, + Iir_Kind_Relative_Pathname => 1719, + Iir_Kind_Pathname_Element => 1724, + Iir_Kind_Base_Attribute => 1726, + Iir_Kind_Subtype_Attribute => 1731, + Iir_Kind_Element_Attribute => 1736, + Iir_Kind_Left_Type_Attribute => 1741, + Iir_Kind_Right_Type_Attribute => 1746, + Iir_Kind_High_Type_Attribute => 1751, + Iir_Kind_Low_Type_Attribute => 1756, + Iir_Kind_Ascending_Type_Attribute => 1761, + Iir_Kind_Image_Attribute => 1767, + Iir_Kind_Value_Attribute => 1773, + Iir_Kind_Pos_Attribute => 1779, + Iir_Kind_Val_Attribute => 1785, + Iir_Kind_Succ_Attribute => 1791, + Iir_Kind_Pred_Attribute => 1797, + Iir_Kind_Leftof_Attribute => 1803, + Iir_Kind_Rightof_Attribute => 1809, + Iir_Kind_Delayed_Attribute => 1818, + Iir_Kind_Stable_Attribute => 1827, + Iir_Kind_Quiet_Attribute => 1836, + Iir_Kind_Transaction_Attribute => 1845, + Iir_Kind_Event_Attribute => 1849, + Iir_Kind_Active_Attribute => 1853, + Iir_Kind_Last_Event_Attribute => 1857, + Iir_Kind_Last_Active_Attribute => 1861, + Iir_Kind_Last_Value_Attribute => 1865, + Iir_Kind_Driving_Attribute => 1869, + Iir_Kind_Driving_Value_Attribute => 1873, + Iir_Kind_Behavior_Attribute => 1873, + Iir_Kind_Structure_Attribute => 1873, + Iir_Kind_Simple_Name_Attribute => 1880, + Iir_Kind_Instance_Name_Attribute => 1885, + Iir_Kind_Path_Name_Attribute => 1890, + Iir_Kind_Left_Array_Attribute => 1897, + Iir_Kind_Right_Array_Attribute => 1904, + Iir_Kind_High_Array_Attribute => 1911, + Iir_Kind_Low_Array_Attribute => 1918, + Iir_Kind_Length_Array_Attribute => 1925, + Iir_Kind_Ascending_Array_Attribute => 1932, + Iir_Kind_Range_Array_Attribute => 1939, + Iir_Kind_Reverse_Range_Array_Attribute => 1946, + Iir_Kind_Attribute_Name => 1955 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -7380,6 +7395,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_Case_Generate_Statement @@ -8158,6 +8174,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_Case_Generate_Statement @@ -8208,6 +8225,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_Case_Generate_Statement @@ -8293,6 +8311,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_Case_Generate_Statement @@ -8759,7 +8778,8 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement => + | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive => return True; when others => return False; @@ -9375,6 +9395,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement | Iir_Kind_Case_Generate_Statement @@ -10731,7 +10752,13 @@ package body Vhdl.Nodes_Meta is function Has_Psl_Sequence (K : Iir_Kind) return Boolean is begin - return K = Iir_Kind_Psl_Cover_Statement; + case K is + when Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive => + return True; + when others => + return False; + end case; end Has_Psl_Sequence; function Has_Psl_Declaration (K : Iir_Kind) return Boolean is @@ -10761,7 +10788,8 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement => + | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive => return True; when others => return False; @@ -10774,7 +10802,8 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement => + | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive => return True; when others => return False; @@ -10786,7 +10815,8 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement => + | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive => return True; when others => return False; @@ -10798,7 +10828,8 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement => + | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive => return True; when others => return False; @@ -10810,7 +10841,8 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement => + | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Restrict_Directive => return True; when others => return False; diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 36750870f..e9230221e 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -8600,7 +8600,7 @@ package body Vhdl.Parse is return Res; end Parse_Psl_Assert_Statement; - function Parse_Psl_Cover_Statement return Iir + function Parse_Psl_Cover_Directive return Iir is Res : Iir; begin @@ -8614,7 +8614,26 @@ package body Vhdl.Parse is Parse_Psl_Assert_Report_Severity (Res); return Res; - end Parse_Psl_Cover_Statement; + end Parse_Psl_Cover_Directive; + + function Parse_Psl_Restrict_Directive return Iir + is + Res : Iir; + begin + Res := Create_Iir (Iir_Kind_Psl_Restrict_Directive); + + -- Skip 'restrict' + Scan; + + Set_Psl_Sequence (Res, Parse_Psl.Parse_Psl_Sequence (True)); + + -- No more PSL tokens after the sequence. + Vhdl.Scanner.Flag_Psl := False; + Vhdl.Scanner.Flag_Scan_In_Comment := False; + + Expect_Scan (Tok_Semi_Colon); + return Res; + end Parse_Psl_Restrict_Directive; -- precond : first token -- postcond: next token (end/else/when...) @@ -8780,7 +8799,10 @@ package body Vhdl.Parse is Stmt := Parse_Psl_Declaration; when Tok_Psl_Cover => Postponed_Not_Allowed; - Stmt := Parse_Psl_Cover_Statement; + Stmt := Parse_Psl_Cover_Directive; + when Tok_Psl_Restrict => + Postponed_Not_Allowed; + Stmt := Parse_Psl_Restrict_Directive; when Tok_Wait | Tok_Loop | Tok_While => diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index a1ce5f01b..2d14bbc2a 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -3892,10 +3892,10 @@ package body Vhdl.Prints is procedure Disp_Psl_Cover_Statement (Ctxt : in out Ctxt_Class; Stmt : Iir) is begin - Start_Hbox (Ctxt); if Vhdl_Std < Vhdl_08 then OOB.Put ("--psl "); end if; + Start_Hbox (Ctxt); Disp_Label (Ctxt, Stmt); Disp_Token (Ctxt, Tok_Psl_Cover); Print_Sequence (Ctxt, Get_Psl_Sequence (Stmt)); @@ -3904,6 +3904,21 @@ package body Vhdl.Prints is Disp_PSL_NFA (Get_PSL_NFA (Stmt)); end Disp_Psl_Cover_Statement; + procedure Disp_Psl_Restrict_Directive + (Ctxt : in out Ctxt_Class; Stmt : Iir) is + begin + if Vhdl_Std < Vhdl_08 then + OOB.Put ("--psl "); + end if; + Start_Hbox (Ctxt); + Disp_Label (Ctxt, Stmt); + Disp_Token (Ctxt, Tok_Psl_Restrict); + Print_Sequence (Ctxt, Get_Psl_Sequence (Stmt)); + Disp_Token (Ctxt, Tok_Semi_Colon); + Close_Hbox (Ctxt); + Disp_PSL_NFA (Get_PSL_NFA (Stmt)); + end Disp_Psl_Restrict_Directive; + procedure Disp_Simple_Simultaneous_Statement (Ctxt : in out Ctxt_Class; Stmt : Iir) is begin @@ -3951,6 +3966,8 @@ package body Vhdl.Prints is Disp_Psl_Assert_Statement (Ctxt, Stmt); when Iir_Kind_Psl_Cover_Statement => Disp_Psl_Cover_Statement (Ctxt, Stmt); + when Iir_Kind_Psl_Restrict_Directive => + Disp_Psl_Restrict_Directive (Ctxt, Stmt); when Iir_Kind_Simple_Simultaneous_Statement => Disp_Simple_Simultaneous_Statement (Ctxt, Stmt); when others => diff --git a/src/vhdl/vhdl-scanner.adb b/src/vhdl/vhdl-scanner.adb index 2f7f37544..8851b1c8e 100644 --- a/src/vhdl/vhdl-scanner.adb +++ b/src/vhdl/vhdl-scanner.adb @@ -1306,6 +1306,10 @@ package body Vhdl.Scanner is Current_Token := Tok_Psl_Cover; when Std_Names.Name_Default => Current_Token := Tok_Psl_Default; + when Std_Names.Name_Restrict => + Current_Token := Tok_Psl_Restrict; + when Std_Names.Name_Restrict_Guarantee => + Current_Token := Tok_Psl_Restrict_Guarantee; when Std_Names.Name_Inf => Current_Token := Tok_Inf; when Std_Names.Name_Within => diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index a1afddd44..4fd0ab2e4 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -750,6 +750,21 @@ package body Vhdl.Sem_Psl is PSL.Subsets.Check_Simple (Seq); end Sem_Psl_Cover_Statement; + procedure Sem_Psl_Restrict_Directive (Stmt : Iir) + is + Seq : PSL_Node; + begin + Seq := Get_Psl_Sequence (Stmt); + Seq := Sem_Sequence (Seq); + + -- Properties must be clocked. + Sem_Psl_Directive_Clock (Stmt, Seq); + Set_Psl_Sequence (Stmt, Seq); + + -- Check simple subset restrictions. + PSL.Subsets.Check_Simple (Seq); + end Sem_Psl_Restrict_Directive; + procedure Sem_Psl_Default_Clock (Stmt : Iir) is Expr : PSL_Node; diff --git a/src/vhdl/vhdl-sem_psl.ads b/src/vhdl/vhdl-sem_psl.ads index 36a20a81c..e4d9c5de1 100644 --- a/src/vhdl/vhdl-sem_psl.ads +++ b/src/vhdl/vhdl-sem_psl.ads @@ -26,6 +26,7 @@ package Vhdl.Sem_Psl is function Sem_Psl_Assert_Statement (Stmt : Iir) return Iir; procedure Sem_Psl_Cover_Statement (Stmt : Iir); + procedure Sem_Psl_Restrict_Directive (Stmt : Iir); procedure Sem_Psl_Default_Clock (Stmt : Iir); function Sem_Psl_Name (Name : Iir) return Iir; end Vhdl.Sem_Psl; diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index 26f412c62..5e9ca55ba 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -2021,6 +2021,8 @@ package body Vhdl.Sem_Stmts is New_El := Sem_Psl.Sem_Psl_Assert_Statement (El); when Iir_Kind_Psl_Cover_Statement => Sem_Psl.Sem_Psl_Cover_Statement (El); + when Iir_Kind_Psl_Restrict_Directive => + Sem_Psl.Sem_Psl_Restrict_Directive (El); when Iir_Kind_Psl_Default_Clock => Sem_Psl.Sem_Psl_Default_Clock (El); when Iir_Kind_Simple_Simultaneous_Statement => diff --git a/src/vhdl/vhdl-tokens.adb b/src/vhdl/vhdl-tokens.adb index fe20a07bd..8ad0e4081 100644 --- a/src/vhdl/vhdl-tokens.adb +++ b/src/vhdl/vhdl-tokens.adb @@ -424,6 +424,10 @@ package body Vhdl.Tokens is return "endpoint"; when Tok_Psl_Cover => return "cover"; + when Tok_Psl_Restrict => + return "restrict"; + when Tok_Psl_Restrict_Guarantee => + return "restrict_guarantee"; when Tok_Psl_Const => return "const"; when Tok_Psl_Boolean => diff --git a/src/vhdl/vhdl-tokens.ads b/src/vhdl/vhdl-tokens.ads index 08834a575..e8daf0bce 100644 --- a/src/vhdl/vhdl-tokens.ads +++ b/src/vhdl/vhdl-tokens.ads @@ -262,6 +262,8 @@ package Vhdl.Tokens is Tok_Psl_Sequence, Tok_Psl_Endpoint, Tok_Psl_Cover, + Tok_Psl_Restrict, + Tok_Psl_Restrict_Guarantee, Tok_Psl_Const, Tok_Psl_Boolean, |