diff options
| -rw-r--r-- | python/libghdl/thin/errorout.py | 9 | ||||
| -rw-r--r-- | python/libghdl/thin/std_names.py | 363 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 101 | ||||
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 7 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 14 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-math_real.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 1 |
8 files changed, 260 insertions, 238 deletions
diff --git a/python/libghdl/thin/errorout.py b/python/libghdl/thin/errorout.py index 36f482c7b..58ba48f4d 100644 --- a/python/libghdl/thin/errorout.py +++ b/python/libghdl/thin/errorout.py @@ -29,7 +29,8 @@ class Msgid: Warnid_Unused = 21 Warnid_Others = 22 Warnid_Pure = 23 - Warnid_Static = 24 - Msgid_Warning = 25 - Msgid_Error = 26 - Msgid_Fatal = 27 + Warnid_Analyze_Assert = 24 + Warnid_Static = 25 + Msgid_Warning = 26 + Msgid_Error = 27 + Msgid_Fatal = 28 diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index 0b98b88b3..5f3143531 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -598,184 +598,185 @@ class Name: Conv_Integer = 812 Math_Real = 813 Ceil = 814 - Log2 = 815 - Sin = 816 - Cos = 817 - Last_Ieee = 817 - First_Synthesis = 818 - Allconst = 818 - Allseq = 819 - Anyconst = 820 - Anyseq = 821 - Last_Synthesis = 821 - First_Directive = 822 - Define = 822 - Endif = 823 - Ifdef = 824 - Ifndef = 825 - Include = 826 - Timescale = 827 - Undef = 828 - Protect = 829 - Begin_Protected = 830 - End_Protected = 831 - Key_Block = 832 - Data_Block = 833 - Line = 834 - Celldefine = 835 - Endcelldefine = 836 - Default_Nettype = 837 - Resetall = 838 - Last_Directive = 838 - First_Systask = 839 - Bits = 839 - D_Root = 840 - D_Unit = 841 - Last_Systask = 841 - First_SV_Method = 842 - Size = 842 - Insert = 843 - Delete = 844 - Pop_Front = 845 - Pop_Back = 846 - Push_Front = 847 - Push_Back = 848 - Name = 849 - Len = 850 - Substr = 851 - Exists = 852 - Atoi = 853 - Itoa = 854 - Find = 855 - Find_Index = 856 - Find_First = 857 - Find_First_Index = 858 - Find_Last = 859 - Find_Last_Index = 860 - Num = 861 - Randomize = 862 - Pre_Randomize = 863 - Post_Randomize = 864 - Srandom = 865 - Get_Randstate = 866 - Set_Randstate = 867 - Seed = 868 - State = 869 - Last_SV_Method = 869 - First_BSV = 870 - uAction = 870 - uActionValue = 871 - BVI = 872 - uC = 873 - uCF = 874 - uE = 875 - uSB = 876 - uSBR = 877 - Action = 878 - Endaction = 879 - Actionvalue = 880 - Endactionvalue = 881 - Ancestor = 882 - Clocked_By = 883 - Default_Clock = 884 - Default_Reset = 885 - Dependencies = 886 - Deriving = 887 - Determines = 888 - Enable = 889 - Ifc_Inout = 890 - Input_Clock = 891 - Input_Reset = 892 - Instance = 893 - Endinstance = 894 - Let = 895 - Match = 896 - Method = 897 - Endmethod = 898 - Numeric = 899 - Output_Clock = 900 - Output_Reset = 901 - Par = 902 - Endpar = 903 - Path = 904 - Provisos = 905 - Ready = 906 - Reset_By = 907 - Rule = 908 - Endrule = 909 - Rules = 910 - Endrules = 911 - Same_Family = 912 - Schedule = 913 - Seq = 914 - Endseq = 915 - Typeclass = 916 - Endtypeclass = 917 - Valueof = 918 - uValueof = 919 - Last_BSV = 919 - First_Comment = 920 - Psl = 920 - Pragma = 921 - Synthesis = 922 - Synopsys = 923 - Translate_Off = 924 - Translate_On = 925 - Last_Comment = 925 - First_PSL = 926 - A = 926 - Af = 927 - Ag = 928 - Ax = 929 - Abort = 930 - Assume_Guarantee = 931 - Before = 932 - Clock = 933 - E = 934 - Ef = 935 - Eg = 936 - Ex = 937 - Endpoint = 938 - Eventually = 939 - Fairness = 940 - Fell = 941 - Forall = 942 - G = 943 - Inf = 944 - Inherit = 945 - Never = 946 - Next_A = 947 - Next_E = 948 - Next_Event = 949 - Next_Event_A = 950 - Next_Event_E = 951 - Prev = 952 - Rose = 953 - Strong = 954 - W = 955 - Whilenot = 956 - Within = 957 - X = 958 - Last_PSL = 958 - First_Edif = 959 - Celltype = 969 - View = 970 - Viewtype = 971 - Direction = 972 - Contents = 973 - Net = 974 - Viewref = 975 - Cellref = 976 - Libraryref = 977 - Portinstance = 978 - Joined = 979 - Portref = 980 - Instanceref = 981 - Design = 982 - Designator = 983 - Owner = 984 - Member = 985 - Number = 986 - Rename = 987 - Userdata = 988 - Last_Edif = 988 + Round = 815 + Log2 = 816 + Sin = 817 + Cos = 818 + Last_Ieee = 818 + First_Synthesis = 819 + Allconst = 819 + Allseq = 820 + Anyconst = 821 + Anyseq = 822 + Last_Synthesis = 822 + First_Directive = 823 + Define = 823 + Endif = 824 + Ifdef = 825 + Ifndef = 826 + Include = 827 + Timescale = 828 + Undef = 829 + Protect = 830 + Begin_Protected = 831 + End_Protected = 832 + Key_Block = 833 + Data_Block = 834 + Line = 835 + Celldefine = 836 + Endcelldefine = 837 + Default_Nettype = 838 + Resetall = 839 + Last_Directive = 839 + First_Systask = 840 + Bits = 840 + D_Root = 841 + D_Unit = 842 + Last_Systask = 842 + First_SV_Method = 843 + Size = 843 + Insert = 844 + Delete = 845 + Pop_Front = 846 + Pop_Back = 847 + Push_Front = 848 + Push_Back = 849 + Name = 850 + Len = 851 + Substr = 852 + Exists = 853 + Atoi = 854 + Itoa = 855 + Find = 856 + Find_Index = 857 + Find_First = 858 + Find_First_Index = 859 + Find_Last = 860 + Find_Last_Index = 861 + Num = 862 + Randomize = 863 + Pre_Randomize = 864 + Post_Randomize = 865 + Srandom = 866 + Get_Randstate = 867 + Set_Randstate = 868 + Seed = 869 + State = 870 + Last_SV_Method = 870 + First_BSV = 871 + uAction = 871 + uActionValue = 872 + BVI = 873 + uC = 874 + uCF = 875 + uE = 876 + uSB = 877 + uSBR = 878 + Action = 879 + Endaction = 880 + Actionvalue = 881 + Endactionvalue = 882 + Ancestor = 883 + Clocked_By = 884 + Default_Clock = 885 + Default_Reset = 886 + Dependencies = 887 + Deriving = 888 + Determines = 889 + Enable = 890 + Ifc_Inout = 891 + Input_Clock = 892 + Input_Reset = 893 + Instance = 894 + Endinstance = 895 + Let = 896 + Match = 897 + Method = 898 + Endmethod = 899 + Numeric = 900 + Output_Clock = 901 + Output_Reset = 902 + Par = 903 + Endpar = 904 + Path = 905 + Provisos = 906 + Ready = 907 + Reset_By = 908 + Rule = 909 + Endrule = 910 + Rules = 911 + Endrules = 912 + Same_Family = 913 + Schedule = 914 + Seq = 915 + Endseq = 916 + Typeclass = 917 + Endtypeclass = 918 + Valueof = 919 + uValueof = 920 + Last_BSV = 920 + First_Comment = 921 + Psl = 921 + Pragma = 922 + Synthesis = 923 + Synopsys = 924 + Translate_Off = 925 + Translate_On = 926 + Last_Comment = 926 + First_PSL = 927 + A = 927 + Af = 928 + Ag = 929 + Ax = 930 + Abort = 931 + Assume_Guarantee = 932 + Before = 933 + Clock = 934 + E = 935 + Ef = 936 + Eg = 937 + Ex = 938 + Endpoint = 939 + Eventually = 940 + Fairness = 941 + Fell = 942 + Forall = 943 + G = 944 + Inf = 945 + Inherit = 946 + Never = 947 + Next_A = 948 + Next_E = 949 + Next_Event = 950 + Next_Event_A = 951 + Next_Event_E = 952 + Prev = 953 + Rose = 954 + Strong = 955 + W = 956 + Whilenot = 957 + Within = 958 + X = 959 + Last_PSL = 959 + First_Edif = 960 + Celltype = 970 + View = 971 + Viewtype = 972 + Direction = 973 + Contents = 974 + Net = 975 + Viewref = 976 + Cellref = 977 + Libraryref = 978 + Portinstance = 979 + Joined = 980 + Portref = 981 + Instanceref = 982 + Design = 983 + Designator = 984 + Owner = 985 + Member = 986 + Number = 987 + Rename = 988 + Userdata = 989 + Last_Edif = 989 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 60e7c2ba4..589d37374 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1283,56 +1283,57 @@ class Iir_Predefined: Ieee_Numeric_Std_Match_Slv = 300 Ieee_Numeric_Std_Match_Suv = 301 Ieee_Math_Real_Ceil = 302 - Ieee_Math_Real_Log2 = 303 - Ieee_Math_Real_Sin = 304 - Ieee_Math_Real_Cos = 305 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 306 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 307 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 308 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 309 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 310 - Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 311 - Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 312 - Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 313 - Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 314 - Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 315 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 316 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 317 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 318 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 319 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 320 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 321 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 322 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 323 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 324 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 325 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 326 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 327 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 328 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 329 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 330 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 331 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 332 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 333 - Ieee_Std_Logic_Unsigned_Conv_Integer = 334 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 335 - Ieee_Std_Logic_Signed_Add_Slv_Int = 336 - Ieee_Std_Logic_Signed_Add_Int_Slv = 337 - Ieee_Std_Logic_Signed_Add_Slv_Sl = 338 - Ieee_Std_Logic_Signed_Add_Sl_Slv = 339 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 340 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 341 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 342 - Ieee_Std_Logic_Signed_Sub_Slv_Sl = 343 - Ieee_Std_Logic_Signed_Sub_Sl_Slv = 344 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 345 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 346 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 347 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 348 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 349 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 350 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 351 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 352 + Ieee_Math_Real_Round = 303 + Ieee_Math_Real_Log2 = 304 + Ieee_Math_Real_Sin = 305 + Ieee_Math_Real_Cos = 306 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 307 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 308 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 309 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 310 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 311 + Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 312 + Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 313 + Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 314 + Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 315 + Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 316 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 317 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 318 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 319 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 320 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 321 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 322 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 323 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 324 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 325 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 326 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 327 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 328 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 329 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 330 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 331 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 332 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 333 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 334 + Ieee_Std_Logic_Unsigned_Conv_Integer = 335 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 336 + Ieee_Std_Logic_Signed_Add_Slv_Int = 337 + Ieee_Std_Logic_Signed_Add_Int_Slv = 338 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 339 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 340 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 341 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 342 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 343 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 344 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 345 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 346 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 347 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 348 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 349 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 350 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 351 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 352 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 353 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index 8c97e5f27..d8d71b29b 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -650,6 +650,7 @@ package body Std_Names is Def ("conv_integer", Name_Conv_Integer); Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); + Def ("round", Name_Round); Def ("log2", Name_Log2); Def ("sin", Name_Sin); Def ("cos", Name_Cos); diff --git a/src/std_names.ads b/src/std_names.ads index f9cc961a0..efb0ba919 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -731,9 +731,10 @@ package Std_Names is Name_Conv_Integer : constant Name_Id := Name_First_Ieee + 032; Name_Math_Real : constant Name_Id := Name_First_Ieee + 033; Name_Ceil : constant Name_Id := Name_First_Ieee + 034; - Name_Log2 : constant Name_Id := Name_First_Ieee + 035; - Name_Sin : constant Name_Id := Name_First_Ieee + 036; - Name_Cos : constant Name_Id := Name_First_Ieee + 037; + Name_Round : constant Name_Id := Name_First_Ieee + 035; + Name_Log2 : constant Name_Id := Name_First_Ieee + 036; + Name_Sin : constant Name_Id := Name_First_Ieee + 037; + Name_Cos : constant Name_Id := Name_First_Ieee + 038; Name_Last_Ieee : constant Name_Id := Name_Cos; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee + 1; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index fcd11201e..471d82979 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1186,6 +1186,20 @@ package body Synth.Oper is return Create_Value_Float (Ceil (V.Fp), Get_Value_Type (Syn_Inst, Get_Type (Imp))); end; + when Iir_Predefined_Ieee_Math_Real_Round => + declare + V : constant Value_Acc := Get_Value (Subprg_Inst, Param1); + + function Round (Arg : Fp64) return Fp64; + pragma Import (C, Round); + begin + if V.Typ.Kind /= Type_Float then + Error_Msg_Synth(+Expr, "argument must be a float value"); + return null; + end if; + return Create_Value_Float + (Round (V.Fp), Get_Value_Type (Syn_Inst, Get_Type (Imp))); + end; when Iir_Predefined_Ieee_Math_Real_Sin => declare V : constant Value_Acc := Get_Value (Subprg_Inst, Param1); diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index 1ac5a9b10..d4f83e62c 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -42,6 +42,8 @@ package body Vhdl.Ieee.Math_Real is case Get_Identifier (Decl) is when Name_Ceil => Predef := Iir_Predefined_Ieee_Math_Real_Ceil; + when Name_Round => + Predef := Iir_Predefined_Ieee_Math_Real_Round; when Name_Log2 => Predef := Iir_Predefined_Ieee_Math_Real_Log2; when Name_Sin => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 4ed10957d..15e21d738 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5593,6 +5593,7 @@ package Vhdl.Nodes is -- Math_Real Iir_Predefined_Ieee_Math_Real_Ceil, + Iir_Predefined_Ieee_Math_Real_Round, Iir_Predefined_Ieee_Math_Real_Log2, Iir_Predefined_Ieee_Math_Real_Sin, Iir_Predefined_Ieee_Math_Real_Cos, |