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-rw-r--r--src/synth/netlists-disp_verilog.adb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb
index 3097e758a..47fa0047a 100644
--- a/src/synth/netlists-disp_verilog.adb
+++ b/src/synth/netlists-disp_verilog.adb
@@ -246,13 +246,14 @@ package body Netlists.Disp_Verilog is
-- Outputs
Idx := 0;
for O of Outputs (Inst) loop
+ Desc := Get_Output_Desc (Imod, Idx);
if First then
First := False;
else
Put_Line (",");
end if;
Put (" .");
- Put_Interface_Name (Get_Output_Desc (Imod, Idx).Name);
+ Put_Interface_Name (Desc.Name);
Idx := Idx + 1;
Put ("(");
declare