diff options
| -rw-r--r-- | testsuite/synth/issue1731/ent.vhdl | 20 | ||||
| -rwxr-xr-x | testsuite/synth/issue1731/testsuite.sh | 4 |
2 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/issue1731/ent.vhdl b/testsuite/synth/issue1731/ent.vhdl new file mode 100644 index 000000000..8170f1f86 --- /dev/null +++ b/testsuite/synth/issue1731/ent.vhdl @@ -0,0 +1,20 @@ +library ieee; +context ieee.ieee_std_context; + +entity ent is + port ( + dsin : in signed(15 downto 0); + dsout : out signed(31 downto 0); + duin : in unsigned(15 downto 0); + duout : out unsigned(31 downto 0) + ); +end; + +architecture arch of ent is + +begin + + dsout <= resize(signed(dsin), dsout); + duout <= resize(unsigned(duin), duout); + +end architecture; diff --git a/testsuite/synth/issue1731/testsuite.sh b/testsuite/synth/issue1731/testsuite.sh index 557967b15..196cc2b74 100755 --- a/testsuite/synth/issue1731/testsuite.sh +++ b/testsuite/synth/issue1731/testsuite.sh @@ -6,6 +6,10 @@ GHDL_STD_FLAGS=--std=08 synth -gfifo_depth=3 fifo.vhdl axis_conv1d9x1.vhdl -e > syn_axi_conv1d9x1.vhdl analyze syn_axi_conv1d9x1.vhdl + +synth ent.vhdl -e > syn_ent.vhdl +analyze syn_ent.vhdl + clean echo "Test successful" |