diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 4 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes_meta.py | 6 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 114 | ||||
| -rw-r--r-- | src/synth/synth-expr.ads | 7 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 68 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.adb | 16 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 18 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes_meta.adb | 272 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes_meta.ads | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_expr.adb | 86 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 60 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.ads | 5 | ||||
| -rw-r--r-- | src/vhdl/vhdl-std_package.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-std_package.ads | 11 |
14 files changed, 441 insertions, 236 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index aebd73dad..04aa11dcb 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -3005,6 +3005,6 @@ Get_Clock_Expression = libghdl.vhdl__nodes__get_clock_expression Set_Clock_Expression = libghdl.vhdl__nodes__set_clock_expression -Get_Clock = libghdl.vhdl__nodes__get_clock +Get_Default_Clock = libghdl.vhdl__nodes__get_default_clock -Set_Clock = libghdl.vhdl__nodes__set_clock +Set_Default_Clock = libghdl.vhdl__nodes__set_default_clock diff --git a/python/libghdl/thin/vhdl/nodes_meta.py b/python/libghdl/thin/vhdl/nodes_meta.py index 83af5ee91..e7d5dd26f 100644 --- a/python/libghdl/thin/vhdl/nodes_meta.py +++ b/python/libghdl/thin/vhdl/nodes_meta.py @@ -424,7 +424,7 @@ class fields: PSL_EOS_Flag = 359 Count_Expression = 360 Clock_Expression = 361 - Clock = 362 + Default_Clock = 362 Get_Boolean = libghdl.vhdl__nodes_meta__get_boolean @@ -1578,5 +1578,5 @@ Has_Count_Expression =\ Has_Clock_Expression =\ libghdl.vhdl__nodes_meta__has_clock_expression -Has_Clock =\ - libghdl.vhdl__nodes_meta__has_clock +Has_Default_Clock =\ + libghdl.vhdl__nodes_meta__has_default_clock diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 123cbd06d..677df4454 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -24,6 +24,7 @@ with Std_Names; with Str_Table; with Mutils; use Mutils; +with Vhdl.Types; with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164; with Vhdl.Std_Package; with Vhdl.Errors; use Vhdl.Errors; @@ -31,9 +32,13 @@ with Vhdl.Utils; use Vhdl.Utils; with Vhdl.Evaluation; use Vhdl.Evaluation; with Vhdl.Annotations; use Vhdl.Annotations; +with PSL.Nodes; +with PSL.Errors; + with Netlists.Gates; use Netlists.Gates; with Netlists.Folds; use Netlists.Folds; with Netlists.Utils; use Netlists.Utils; +with Netlists.Locations; with Synth.Errors; use Synth.Errors; with Synth.Environment; @@ -1779,6 +1784,113 @@ package body Synth.Expr is return Create_Value_Discrete (R, Typ); end Synth_Low_High_Type_Attribute; + function Synth_PSL_Expression + (Syn_Inst : Synth_Instance_Acc; Expr : PSL.Types.PSL_Node) return Net + is + use PSL.Types; + use PSL.Nodes; + + Ctxt : constant Context_Acc := Get_Build (Syn_Inst); + Loc : constant Location_Type := Get_Location (Expr); + Res : Net; + begin + case Get_Kind (Expr) is + when N_HDL_Bool => + declare + E : constant Vhdl.Types.Vhdl_Node := Get_HDL_Node (Expr); + begin + return Get_Net (Ctxt, Synth_Expression (Syn_Inst, E)); + end; + when N_Not_Bool => + pragma Assert (Loc /= No_Location); + Res := Build_Monadic + (Ctxt, Id_Not, + Synth_PSL_Expression (Syn_Inst, Get_Boolean (Expr))); + when N_And_Bool => + pragma Assert (Loc /= No_Location); + declare + L : constant PSL_Node := Get_Left (Expr); + R : constant PSL_Node := Get_Right (Expr); + Edge : Net; + begin + -- Handle edge (as it can be in default clock). + if Get_Kind (L) in N_HDLs and then Get_Kind (R) in N_HDLs then + Edge := Synth_Clock_Edge + (Syn_Inst, Get_HDL_Node (L), Get_HDL_Node (R)); + if Edge /= No_Net then + return Edge; + end if; + end if; + if Get_Kind (R) = N_EOS then + -- It is never EOS! + Res := Build_Const_UB32 (Ctxt, 0, 1); + else + Res := Build_Dyadic (Ctxt, Id_And, + Synth_PSL_Expression (Syn_Inst, L), + Synth_PSL_Expression (Syn_Inst, R)); + end if; + end; + when N_Or_Bool => + pragma Assert (Loc /= No_Location); + Res := Build_Dyadic + (Ctxt, Id_Or, + Synth_PSL_Expression (Syn_Inst, Get_Left (Expr)), + Synth_PSL_Expression (Syn_Inst, Get_Right (Expr))); + when N_True => + Res := Build_Const_UB32 (Ctxt, 1, 1); + when N_False + | N_EOS => + Res := Build_Const_UB32 (Ctxt, 0, 1); + when others => + PSL.Errors.Error_Kind ("synth_psl_expr", Expr); + return No_Net; + end case; + Netlists.Locations.Set_Location (Get_Net_Parent (Res), Loc); + return Res; + end Synth_PSL_Expression; + + function Synth_Psl_Prev (Syn_Inst : Synth_Instance_Acc; Call : Node) + return Valtyp + is + Ctxt : constant Context_Acc := Get_Build (Syn_Inst); + Count : constant Node := Get_Count_Expression (Call); + Clock : Node; + Count_Val : Valtyp; + Dff : Net; + Clk : Valtyp; + Expr : Valtyp; + Clk_Net : Net; + Num : Int64; + begin + Expr := Synth_Expression (Syn_Inst, Get_Expression (Call)); + + Clock := Get_Clock_Expression (Call); + if Clock /= Null_Node then + Clk := Synth_Expression (Syn_Inst, Clock); + Clk_Net := Get_Net (Ctxt, Clk); + else + Clock := Get_Default_Clock (Call); + pragma Assert (Clock /= Null_Node); + Clk_Net := Synth_PSL_Expression (Syn_Inst, Get_Psl_Boolean (Clock)); + end if; + + if Count /= Null_Node then + Count_Val := Synth_Expression (Syn_Inst, Count); + Num := Read_Discrete (Count_Val); + pragma Assert (Num >= 1); + else + Num := 1; + end if; + + Dff := Get_Net (Ctxt, Expr); + for I in 1 .. Num loop + Dff := Build_Dff (Ctxt, Clk_Net, Dff); + Set_Location (Dff, Call); + end loop; + + return Create_Value_Net (Dff, Expr.Typ); + end Synth_Psl_Prev; + subtype And_Or_Module_Id is Module_Id range Id_And .. Id_Or; function Synth_Short_Circuit (Syn_Inst : Synth_Instance_Acc; @@ -2117,6 +2229,8 @@ package body Synth.Expr is when Iir_Kind_Stable_Attribute => Error_Msg_Synth (+Expr, "signal attribute not supported"); return No_Valtyp; + when Iir_Kind_Psl_Prev => + return Synth_Psl_Prev (Syn_Inst, Expr); when Iir_Kind_Overflow_Literal => Error_Msg_Synth (+Expr, "out of bound expression"); return No_Valtyp; diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads index 1da15ce29..481062a0a 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-expr.ads @@ -22,6 +22,9 @@ with Ada.Unchecked_Deallocation; with Types; use Types; +with PSL.Types; +with Vhdl.Nodes; use Vhdl.Nodes; + with Netlists; use Netlists; with Netlists.Builders; use Netlists.Builders; @@ -29,7 +32,6 @@ with Synth.Source; with Synth.Objtypes; use Synth.Objtypes; with Synth.Values; use Synth.Values; with Synth.Context; use Synth.Context; -with Vhdl.Nodes; use Vhdl.Nodes; package Synth.Expr is -- Perform a subtype conversion. Check constraints. @@ -90,6 +92,9 @@ package Synth.Expr is function Synth_Expression_With_Basetype (Syn_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp; + function Synth_PSL_Expression + (Syn_Inst : Synth_Instance_Acc; Expr : PSL.Types.PSL_Node) return Net; + function Synth_Bounds_From_Range (Syn_Inst : Synth_Instance_Acc; Atype : Node) return Bound_Type; diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 210d4b04f..a7b8dc232 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -31,7 +31,6 @@ with Files_Map; with Simple_IO; with Vhdl.Errors; use Vhdl.Errors; -with Vhdl.Types; with Vhdl.Sem_Expr; with Vhdl.Sem_Inst; with Vhdl.Utils; use Vhdl.Utils; @@ -40,9 +39,7 @@ with Vhdl.Evaluation; with Vhdl.Ieee.Std_Logic_1164; with PSL.Types; -with PSL.Nodes; with PSL.NFAs; -with PSL.Errors; with Synth.Errors; use Synth.Errors; with Synth.Decls; use Synth.Decls; @@ -3115,71 +3112,6 @@ package body Synth.Stmts is Instance_Pool := Prev_Instance_Pool; end Synth_Block_Statement; - function Synth_PSL_Expression - (Syn_Inst : Synth_Instance_Acc; Expr : PSL.Types.PSL_Node) return Net - is - use PSL.Types; - use PSL.Nodes; - - Ctxt : constant Context_Acc := Get_Build (Syn_Inst); - Loc : constant Location_Type := Get_Location (Expr); - Res : Net; - begin - case Get_Kind (Expr) is - when N_HDL_Bool => - declare - E : constant Vhdl.Types.Vhdl_Node := Get_HDL_Node (Expr); - begin - return Get_Net (Ctxt, Synth_Expression (Syn_Inst, E)); - end; - when N_Not_Bool => - pragma Assert (Loc /= No_Location); - Res := Build_Monadic - (Ctxt, Id_Not, - Synth_PSL_Expression (Syn_Inst, Get_Boolean (Expr))); - when N_And_Bool => - pragma Assert (Loc /= No_Location); - declare - L : constant PSL_Node := Get_Left (Expr); - R : constant PSL_Node := Get_Right (Expr); - Edge : Net; - begin - -- Handle edge (as it can be in default clock). - if Get_Kind (L) in N_HDLs and then Get_Kind (R) in N_HDLs then - Edge := Synth_Clock_Edge - (Syn_Inst, Get_HDL_Node (L), Get_HDL_Node (R)); - if Edge /= No_Net then - return Edge; - end if; - end if; - if Get_Kind (R) = N_EOS then - -- It is never EOS! - Res := Build_Const_UB32 (Ctxt, 0, 1); - else - Res := Build_Dyadic (Ctxt, Id_And, - Synth_PSL_Expression (Syn_Inst, L), - Synth_PSL_Expression (Syn_Inst, R)); - end if; - end; - when N_Or_Bool => - pragma Assert (Loc /= No_Location); - Res := Build_Dyadic - (Ctxt, Id_Or, - Synth_PSL_Expression (Syn_Inst, Get_Left (Expr)), - Synth_PSL_Expression (Syn_Inst, Get_Right (Expr))); - when N_True => - Res := Build_Const_UB32 (Ctxt, 1, 1); - when N_False - | N_EOS => - Res := Build_Const_UB32 (Ctxt, 0, 1); - when others => - PSL.Errors.Error_Kind ("synth_psl_expr", Expr); - return No_Net; - end case; - Set_Location (Res, Loc); - return Res; - end Synth_PSL_Expression; - function Synth_Psl_NFA (Syn_Inst : Synth_Instance_Acc; NFA : PSL.Types.PSL_NFA; Nbr_States : Int32; diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index c28146a4e..5501cec1a 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -7216,20 +7216,20 @@ package body Vhdl.Nodes is Set_Field4 (N, Clk); end Set_Clock_Expression; - function Get_Clock (N : Iir) return Iir is + function Get_Default_Clock (N : Iir) return Iir is begin pragma Assert (N /= Null_Iir); - pragma Assert (Has_Clock (Get_Kind (N)), - "no field Clock"); + pragma Assert (Has_Default_Clock (Get_Kind (N)), + "no field Default_Clock"); return Get_Field3 (N); - end Get_Clock; + end Get_Default_Clock; - procedure Set_Clock (N : Iir; Clk : Iir) is + procedure Set_Default_Clock (N : Iir; Clk : Iir) is begin pragma Assert (N /= Null_Iir); - pragma Assert (Has_Clock (Get_Kind (N)), - "no field Clock"); + pragma Assert (Has_Default_Clock (Get_Kind (N)), + "no field Default_Clock"); Set_Field3 (N, Clk); - end Set_Clock; + end Set_Default_Clock; end Vhdl.Nodes; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 0965b5388..05cbcf576 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -856,8 +856,10 @@ package Vhdl.Nodes is -- -- Get/Set_Clock_Expression (Field4) -- - -- Reference to the clock node (can be the default one). - -- Get/Set_Clock (Field3) + -- Reference to the default_clock node. + -- Get/Set_Default_Clock (Field3) + -- + -- Get/Set_Expr_Staticness (State1) -- Iir_Kind_Psl_Stable (Short) -- Iir_Kind_Psl_Rose (Short) @@ -869,8 +871,10 @@ package Vhdl.Nodes is -- -- Get/Set_Clock_Expression (Field4) -- - -- Reference to the clock node (can be the default one). - -- Get/Set_Clock (Field3) + -- Reference to the defult_clock node. + -- Get/Set_Default_Clock (Field3) + -- + -- Get/Set_Expr_Staticness (State1) -- Iir_Kind_Signature (Medium) -- @@ -8992,8 +8996,8 @@ package Vhdl.Nodes is function Get_Clock_Expression (N : Iir) return Iir; procedure Set_Clock_Expression (N : Iir; Clk : Iir); - -- Reference to the clock node (can be the default one). + -- Reference to the default_clock node. -- Field: Field3 Ref - function Get_Clock (N : Iir) return Iir; - procedure Set_Clock (N : Iir; Clk : Iir); + function Get_Default_Clock (N : Iir) return Iir; + procedure Set_Default_Clock (N : Iir; Clk : Iir); end Vhdl.Nodes; diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index 086ce4c78..c64eed50b 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -381,7 +381,7 @@ package body Vhdl.Nodes_Meta is Field_PSL_EOS_Flag => Type_Boolean, Field_Count_Expression => Type_Iir, Field_Clock_Expression => Type_Iir, - Field_Clock => Type_Iir + Field_Default_Clock => Type_Iir ); function Get_Field_Type (F : Fields_Enum) return Types_Enum is @@ -1116,8 +1116,8 @@ package body Vhdl.Nodes_Meta is return "count_expression"; when Field_Clock_Expression => return "clock_expression"; - when Field_Clock => - return "clock"; + when Field_Default_Clock => + return "default_clock"; end case; end Get_Field_Image; @@ -2476,7 +2476,7 @@ package body Vhdl.Nodes_Meta is return Attr_None; when Field_Clock_Expression => return Attr_None; - when Field_Clock => + when Field_Default_Clock => return Attr_Ref; end case; end Get_Field_Attribute; @@ -4143,26 +4143,30 @@ package body Vhdl.Nodes_Meta is Field_Index_List, Field_Base_Name, -- Iir_Kind_Psl_Prev + Field_Expr_Staticness, Field_Type, Field_Expression, Field_Count_Expression, Field_Clock_Expression, - Field_Clock, + Field_Default_Clock, -- Iir_Kind_Psl_Stable + Field_Expr_Staticness, Field_Type, Field_Expression, Field_Clock_Expression, - Field_Clock, + Field_Default_Clock, -- Iir_Kind_Psl_Rose + Field_Expr_Staticness, Field_Type, Field_Expression, Field_Clock_Expression, - Field_Clock, + Field_Default_Clock, -- Iir_Kind_Psl_Fell + Field_Expr_Staticness, Field_Type, Field_Expression, Field_Clock_Expression, - Field_Clock, + Field_Default_Clock, -- Iir_Kind_Psl_Expression Field_Psl_Expression, Field_Type, @@ -5308,124 +5312,124 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Implicit_Dereference => 1452, Iir_Kind_Slice_Name => 1459, Iir_Kind_Indexed_Name => 1465, - Iir_Kind_Psl_Prev => 1470, - Iir_Kind_Psl_Stable => 1474, - Iir_Kind_Psl_Rose => 1478, - Iir_Kind_Psl_Fell => 1482, - Iir_Kind_Psl_Expression => 1484, - Iir_Kind_Sensitized_Process_Statement => 1505, - Iir_Kind_Process_Statement => 1525, - Iir_Kind_Concurrent_Simple_Signal_Assignment => 1538, - Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1551, - Iir_Kind_Concurrent_Selected_Signal_Assignment => 1565, - Iir_Kind_Concurrent_Assertion_Statement => 1573, - Iir_Kind_Concurrent_Procedure_Call_Statement => 1580, - Iir_Kind_Concurrent_Break_Statement => 1588, - Iir_Kind_Psl_Assert_Directive => 1601, - Iir_Kind_Psl_Assume_Directive => 1612, - Iir_Kind_Psl_Cover_Directive => 1624, - Iir_Kind_Psl_Restrict_Directive => 1635, - Iir_Kind_Block_Statement => 1649, - Iir_Kind_If_Generate_Statement => 1660, - Iir_Kind_Case_Generate_Statement => 1669, - Iir_Kind_For_Generate_Statement => 1678, - Iir_Kind_Component_Instantiation_Statement => 1689, - Iir_Kind_Psl_Default_Clock => 1693, - Iir_Kind_Generate_Statement_Body => 1704, - Iir_Kind_If_Generate_Else_Clause => 1710, - Iir_Kind_Simple_Simultaneous_Statement => 1717, - Iir_Kind_Simultaneous_Null_Statement => 1721, - Iir_Kind_Simultaneous_Procedural_Statement => 1732, - Iir_Kind_Simultaneous_Case_Statement => 1741, - Iir_Kind_Simultaneous_If_Statement => 1750, - Iir_Kind_Simultaneous_Elsif => 1756, - Iir_Kind_Simple_Signal_Assignment_Statement => 1767, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1778, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1790, - Iir_Kind_Null_Statement => 1794, - Iir_Kind_Assertion_Statement => 1801, - Iir_Kind_Report_Statement => 1807, - Iir_Kind_Wait_Statement => 1815, - Iir_Kind_Variable_Assignment_Statement => 1822, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1829, - Iir_Kind_Return_Statement => 1835, - Iir_Kind_For_Loop_Statement => 1846, - Iir_Kind_While_Loop_Statement => 1857, - Iir_Kind_Next_Statement => 1864, - Iir_Kind_Exit_Statement => 1871, - Iir_Kind_Case_Statement => 1879, - Iir_Kind_Procedure_Call_Statement => 1885, - Iir_Kind_Break_Statement => 1892, - Iir_Kind_If_Statement => 1902, - Iir_Kind_Elsif => 1908, - Iir_Kind_Character_Literal => 1916, - Iir_Kind_Simple_Name => 1924, - Iir_Kind_Selected_Name => 1933, - Iir_Kind_Operator_Symbol => 1939, - Iir_Kind_Reference_Name => 1944, - Iir_Kind_External_Constant_Name => 1952, - Iir_Kind_External_Signal_Name => 1960, - Iir_Kind_External_Variable_Name => 1969, - Iir_Kind_Selected_By_All_Name => 1975, - Iir_Kind_Parenthesis_Name => 1980, - Iir_Kind_Package_Pathname => 1984, - Iir_Kind_Absolute_Pathname => 1985, - Iir_Kind_Relative_Pathname => 1986, - Iir_Kind_Pathname_Element => 1991, - Iir_Kind_Base_Attribute => 1993, - Iir_Kind_Subtype_Attribute => 1998, - Iir_Kind_Element_Attribute => 2003, - Iir_Kind_Across_Attribute => 2008, - Iir_Kind_Through_Attribute => 2013, - Iir_Kind_Nature_Reference_Attribute => 2017, - Iir_Kind_Left_Type_Attribute => 2022, - Iir_Kind_Right_Type_Attribute => 2027, - Iir_Kind_High_Type_Attribute => 2032, - Iir_Kind_Low_Type_Attribute => 2037, - Iir_Kind_Ascending_Type_Attribute => 2042, - Iir_Kind_Image_Attribute => 2048, - Iir_Kind_Value_Attribute => 2054, - Iir_Kind_Pos_Attribute => 2060, - Iir_Kind_Val_Attribute => 2066, - Iir_Kind_Succ_Attribute => 2072, - Iir_Kind_Pred_Attribute => 2078, - Iir_Kind_Leftof_Attribute => 2084, - Iir_Kind_Rightof_Attribute => 2090, - Iir_Kind_Signal_Slew_Attribute => 2098, - Iir_Kind_Quantity_Slew_Attribute => 2106, - Iir_Kind_Ramp_Attribute => 2114, - Iir_Kind_Zoh_Attribute => 2122, - Iir_Kind_Ltf_Attribute => 2130, - Iir_Kind_Ztf_Attribute => 2140, - Iir_Kind_Dot_Attribute => 2147, - Iir_Kind_Integ_Attribute => 2154, - Iir_Kind_Above_Attribute => 2162, - Iir_Kind_Quantity_Delayed_Attribute => 2170, - Iir_Kind_Delayed_Attribute => 2179, - Iir_Kind_Stable_Attribute => 2188, - Iir_Kind_Quiet_Attribute => 2197, - Iir_Kind_Transaction_Attribute => 2206, - Iir_Kind_Event_Attribute => 2210, - Iir_Kind_Active_Attribute => 2214, - Iir_Kind_Last_Event_Attribute => 2218, - Iir_Kind_Last_Active_Attribute => 2222, - Iir_Kind_Last_Value_Attribute => 2226, - Iir_Kind_Driving_Attribute => 2230, - Iir_Kind_Driving_Value_Attribute => 2234, - Iir_Kind_Behavior_Attribute => 2234, - Iir_Kind_Structure_Attribute => 2234, - Iir_Kind_Simple_Name_Attribute => 2241, - Iir_Kind_Instance_Name_Attribute => 2246, - Iir_Kind_Path_Name_Attribute => 2251, - Iir_Kind_Left_Array_Attribute => 2258, - Iir_Kind_Right_Array_Attribute => 2265, - Iir_Kind_High_Array_Attribute => 2272, - Iir_Kind_Low_Array_Attribute => 2279, - Iir_Kind_Length_Array_Attribute => 2286, - Iir_Kind_Ascending_Array_Attribute => 2293, - Iir_Kind_Range_Array_Attribute => 2300, - Iir_Kind_Reverse_Range_Array_Attribute => 2307, - Iir_Kind_Attribute_Name => 2316 + Iir_Kind_Psl_Prev => 1471, + Iir_Kind_Psl_Stable => 1476, + Iir_Kind_Psl_Rose => 1481, + Iir_Kind_Psl_Fell => 1486, + Iir_Kind_Psl_Expression => 1488, + Iir_Kind_Sensitized_Process_Statement => 1509, + Iir_Kind_Process_Statement => 1529, + Iir_Kind_Concurrent_Simple_Signal_Assignment => 1542, + Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1555, + Iir_Kind_Concurrent_Selected_Signal_Assignment => 1569, + Iir_Kind_Concurrent_Assertion_Statement => 1577, + Iir_Kind_Concurrent_Procedure_Call_Statement => 1584, + Iir_Kind_Concurrent_Break_Statement => 1592, + Iir_Kind_Psl_Assert_Directive => 1605, + Iir_Kind_Psl_Assume_Directive => 1616, + Iir_Kind_Psl_Cover_Directive => 1628, + Iir_Kind_Psl_Restrict_Directive => 1639, + Iir_Kind_Block_Statement => 1653, + Iir_Kind_If_Generate_Statement => 1664, + Iir_Kind_Case_Generate_Statement => 1673, + Iir_Kind_For_Generate_Statement => 1682, + Iir_Kind_Component_Instantiation_Statement => 1693, + Iir_Kind_Psl_Default_Clock => 1697, + Iir_Kind_Generate_Statement_Body => 1708, + Iir_Kind_If_Generate_Else_Clause => 1714, + Iir_Kind_Simple_Simultaneous_Statement => 1721, + Iir_Kind_Simultaneous_Null_Statement => 1725, + Iir_Kind_Simultaneous_Procedural_Statement => 1736, + Iir_Kind_Simultaneous_Case_Statement => 1745, + Iir_Kind_Simultaneous_If_Statement => 1754, + Iir_Kind_Simultaneous_Elsif => 1760, + Iir_Kind_Simple_Signal_Assignment_Statement => 1771, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1782, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1794, + Iir_Kind_Null_Statement => 1798, + Iir_Kind_Assertion_Statement => 1805, + Iir_Kind_Report_Statement => 1811, + Iir_Kind_Wait_Statement => 1819, + Iir_Kind_Variable_Assignment_Statement => 1826, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1833, + Iir_Kind_Return_Statement => 1839, + Iir_Kind_For_Loop_Statement => 1850, + Iir_Kind_While_Loop_Statement => 1861, + Iir_Kind_Next_Statement => 1868, + Iir_Kind_Exit_Statement => 1875, + Iir_Kind_Case_Statement => 1883, + Iir_Kind_Procedure_Call_Statement => 1889, + Iir_Kind_Break_Statement => 1896, + Iir_Kind_If_Statement => 1906, + Iir_Kind_Elsif => 1912, + Iir_Kind_Character_Literal => 1920, + Iir_Kind_Simple_Name => 1928, + Iir_Kind_Selected_Name => 1937, + Iir_Kind_Operator_Symbol => 1943, + Iir_Kind_Reference_Name => 1948, + Iir_Kind_External_Constant_Name => 1956, + Iir_Kind_External_Signal_Name => 1964, + Iir_Kind_External_Variable_Name => 1973, + Iir_Kind_Selected_By_All_Name => 1979, + Iir_Kind_Parenthesis_Name => 1984, + Iir_Kind_Package_Pathname => 1988, + Iir_Kind_Absolute_Pathname => 1989, + Iir_Kind_Relative_Pathname => 1990, + Iir_Kind_Pathname_Element => 1995, + Iir_Kind_Base_Attribute => 1997, + Iir_Kind_Subtype_Attribute => 2002, + Iir_Kind_Element_Attribute => 2007, + Iir_Kind_Across_Attribute => 2012, + Iir_Kind_Through_Attribute => 2017, + Iir_Kind_Nature_Reference_Attribute => 2021, + Iir_Kind_Left_Type_Attribute => 2026, + Iir_Kind_Right_Type_Attribute => 2031, + Iir_Kind_High_Type_Attribute => 2036, + Iir_Kind_Low_Type_Attribute => 2041, + Iir_Kind_Ascending_Type_Attribute => 2046, + Iir_Kind_Image_Attribute => 2052, + Iir_Kind_Value_Attribute => 2058, + Iir_Kind_Pos_Attribute => 2064, + Iir_Kind_Val_Attribute => 2070, + Iir_Kind_Succ_Attribute => 2076, + Iir_Kind_Pred_Attribute => 2082, + Iir_Kind_Leftof_Attribute => 2088, + Iir_Kind_Rightof_Attribute => 2094, + Iir_Kind_Signal_Slew_Attribute => 2102, + Iir_Kind_Quantity_Slew_Attribute => 2110, + Iir_Kind_Ramp_Attribute => 2118, + Iir_Kind_Zoh_Attribute => 2126, + Iir_Kind_Ltf_Attribute => 2134, + Iir_Kind_Ztf_Attribute => 2144, + Iir_Kind_Dot_Attribute => 2151, + Iir_Kind_Integ_Attribute => 2158, + Iir_Kind_Above_Attribute => 2166, + Iir_Kind_Quantity_Delayed_Attribute => 2174, + Iir_Kind_Delayed_Attribute => 2183, + Iir_Kind_Stable_Attribute => 2192, + Iir_Kind_Quiet_Attribute => 2201, + Iir_Kind_Transaction_Attribute => 2210, + Iir_Kind_Event_Attribute => 2214, + Iir_Kind_Active_Attribute => 2218, + Iir_Kind_Last_Event_Attribute => 2222, + Iir_Kind_Last_Active_Attribute => 2226, + Iir_Kind_Last_Value_Attribute => 2230, + Iir_Kind_Driving_Attribute => 2234, + Iir_Kind_Driving_Value_Attribute => 2238, + Iir_Kind_Behavior_Attribute => 2238, + Iir_Kind_Structure_Attribute => 2238, + Iir_Kind_Simple_Name_Attribute => 2245, + Iir_Kind_Instance_Name_Attribute => 2250, + Iir_Kind_Path_Name_Attribute => 2255, + Iir_Kind_Left_Array_Attribute => 2262, + Iir_Kind_Right_Array_Attribute => 2269, + Iir_Kind_High_Array_Attribute => 2276, + Iir_Kind_Low_Array_Attribute => 2283, + Iir_Kind_Length_Array_Attribute => 2290, + Iir_Kind_Ascending_Array_Attribute => 2297, + Iir_Kind_Range_Array_Attribute => 2304, + Iir_Kind_Reverse_Range_Array_Attribute => 2311, + Iir_Kind_Attribute_Name => 2320 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -6306,8 +6310,8 @@ package body Vhdl.Nodes_Meta is return Get_Count_Expression (N); when Field_Clock_Expression => return Get_Clock_Expression (N); - when Field_Clock => - return Get_Clock (N); + when Field_Default_Clock => + return Get_Default_Clock (N); when others => raise Internal_Error; end case; @@ -6760,8 +6764,8 @@ package body Vhdl.Nodes_Meta is Set_Count_Expression (N, V); when Field_Clock_Expression => Set_Clock_Expression (N, V); - when Field_Clock => - Set_Clock (N, V); + when Field_Default_Clock => + Set_Default_Clock (N, V); when others => raise Internal_Error; end case; @@ -10923,6 +10927,10 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Implicit_Dereference | Iir_Kind_Slice_Name | Iir_Kind_Indexed_Name + | Iir_Kind_Psl_Prev + | Iir_Kind_Psl_Stable + | Iir_Kind_Psl_Rose + | Iir_Kind_Psl_Fell | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name @@ -12375,7 +12383,7 @@ package body Vhdl.Nodes_Meta is end case; end Has_Clock_Expression; - function Has_Clock (K : Iir_Kind) return Boolean is + function Has_Default_Clock (K : Iir_Kind) return Boolean is begin case K is when Iir_Kind_Psl_Prev @@ -12386,6 +12394,6 @@ package body Vhdl.Nodes_Meta is when others => return False; end case; - end Has_Clock; + end Has_Default_Clock; end Vhdl.Nodes_Meta; diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads index 25673bf8e..8fd5644cd 100644 --- a/src/vhdl/vhdl-nodes_meta.ads +++ b/src/vhdl/vhdl-nodes_meta.ads @@ -424,7 +424,7 @@ package Vhdl.Nodes_Meta is Field_PSL_EOS_Flag, Field_Count_Expression, Field_Clock_Expression, - Field_Clock + Field_Default_Clock ); pragma Discard_Names (Fields_Enum); @@ -999,5 +999,5 @@ package Vhdl.Nodes_Meta is function Has_PSL_EOS_Flag (K : Iir_Kind) return Boolean; function Has_Count_Expression (K : Iir_Kind) return Boolean; function Has_Clock_Expression (K : Iir_Kind) return Boolean; - function Has_Clock (K : Iir_Kind) return Boolean; + function Has_Default_Clock (K : Iir_Kind) return Boolean; end Vhdl.Nodes_Meta; diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index 506bf4290..db03456e3 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -21,18 +21,20 @@ with Errorout; use Errorout; with Name_Table; with Str_Table; with Flags; use Flags; + with Vhdl.Std_Package; use Vhdl.Std_Package; -with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes; -with Vhdl.Sem_Names; use Vhdl.Sem_Names; -with Vhdl.Sem; with Vhdl.Errors; use Vhdl.Errors; with Vhdl.Utils; use Vhdl.Utils; with Vhdl.Evaluation; use Vhdl.Evaluation; with Vhdl.Nodes_Utils; use Vhdl.Nodes_Utils; +with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes; +with Vhdl.Sem_Names; use Vhdl.Sem_Names; +with Vhdl.Sem; with Vhdl.Sem_Types; with Vhdl.Sem_Stmts; use Vhdl.Sem_Stmts; with Vhdl.Sem_Assocs; use Vhdl.Sem_Assocs; with Vhdl.Sem_Decls; +with Vhdl.Sem_Psl; with Vhdl.Xrefs; use Vhdl.Xrefs; package body Vhdl.Sem_Expr is @@ -4436,6 +4438,8 @@ package body Vhdl.Sem_Expr is when Iir_Kind_Simple_Name | Iir_Kind_Selected_Name => Obj := Get_Named_Entity (Obj); + when Iir_Kinds_Psl_Builtin => + return; when Iir_Kind_Error => return; when others => @@ -4821,6 +4825,9 @@ package body Vhdl.Sem_Expr is return Create_Error_Expr (Res, A_Type); end; + when Iir_Kind_Psl_Prev => + return Sem_Psl.Sem_Prev_Builtin (Expr, A_Type); + when Iir_Kind_Error => -- Always ok. -- Use the error as a type. @@ -4858,25 +4865,72 @@ package body Vhdl.Sem_Expr is return Wildcard_Any_Aggregate_Type; when Wildcard_Any_String_Type => return Wildcard_Any_String_Type; - when Wildcard_Any_Access_Type => + when Wildcard_Psl_Bitvector_Type => + return Wildcard_Psl_Bitvector_Type; + when Wildcard_Any_Access_Type + | Wildcard_Any_Integer_Type + | Wildcard_Psl_Bit_Type => return Null_Iir; end case; when Wildcard_Any_String_Type => case Iir_Wildcard_Types (Atype) is when Wildcard_Any_Type - | Wildcard_Any_Aggregate_Type - | Wildcard_Any_String_Type => + | Wildcard_Any_Aggregate_Type + | Wildcard_Any_String_Type => return Wildcard_Any_String_Type; - when Wildcard_Any_Access_Type => + when Wildcard_Psl_Bitvector_Type => + return Wildcard_Psl_Bitvector_Type; + when Wildcard_Any_Access_Type + | Wildcard_Any_Integer_Type + | Wildcard_Psl_Bit_Type => return Null_Iir; end case; when Wildcard_Any_Access_Type => case Iir_Wildcard_Types (Atype) is when Wildcard_Any_Type - | Wildcard_Any_Access_Type => + | Wildcard_Any_Access_Type => return Wildcard_Any_Access_Type; when Wildcard_Any_Aggregate_Type - | Wildcard_Any_String_Type => + | Wildcard_Any_String_Type + | Wildcard_Any_Integer_Type + | Wildcard_Psl_Bit_Type + | Wildcard_Psl_Bitvector_Type => + return Null_Iir; + end case; + when Wildcard_Any_Integer_Type => + case Iir_Wildcard_Types (Atype) is + when Wildcard_Any_Type + | Wildcard_Any_Integer_Type => + return Wildcard_Any_Integer_Type; + when Wildcard_Any_Access_Type + | Wildcard_Any_Aggregate_Type + | Wildcard_Any_String_Type + | Wildcard_Psl_Bit_Type + | Wildcard_Psl_Bitvector_Type => + return Null_Iir; + end case; + when Wildcard_Psl_Bit_Type => + case Iir_Wildcard_Types (Atype) is + when Wildcard_Any_Type + | Wildcard_Psl_Bit_Type => + return Wildcard_Psl_Bit_Type; + when Wildcard_Any_Access_Type + | Wildcard_Any_Aggregate_Type + | Wildcard_Any_String_Type + | Wildcard_Any_Integer_Type + | Wildcard_Psl_Bitvector_Type => + return Null_Iir; + end case; + when Wildcard_Psl_Bitvector_Type => + case Iir_Wildcard_Types (Atype) is + when Wildcard_Any_Type + | Wildcard_Any_Aggregate_Type + | Wildcard_Any_String_Type + | Wildcard_Psl_Bitvector_Type => + return Wildcard_Psl_Bitvector_Type; + when Wildcard_Any_Access_Type + | Wildcard_Any_Integer_Type + | Wildcard_Psl_Bit_Type => return Null_Iir; end case; end case; @@ -4899,6 +4953,20 @@ package body Vhdl.Sem_Expr is then return Atype; end if; + when Wildcard_Any_Integer_Type => + if Get_Kind (Get_Base_Type (Atype)) + = Iir_Kind_Integer_Type_Definition + then + return Atype; + end if; + when Wildcard_Psl_Bit_Type => + if Sem_Psl.Is_Psl_Bit_Type (Atype) then + return Atype; + end if; + when Wildcard_Psl_Bitvector_Type => + if Sem_Psl.Is_Psl_Bitvector_Type (Atype) then + return Atype; + end if; end case; return Null_Iir; end if; diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index c97f7a009..c4ebf345e 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -63,6 +63,66 @@ package body Vhdl.Sem_Psl is return Is_Psl_Bool_Type (Get_Type (Expr)); end Is_Psl_Bool_Expr; + function Is_Psl_Bit_Type (Atype : Iir) return Boolean + is + Btype : constant Iir := Get_Base_Type (Atype); + begin + return Btype = Vhdl.Std_Package.Bit_Type_Definition + or else Btype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type; + end Is_Psl_Bit_Type; + + function Is_Psl_Bitvector_Type (Atype : Iir) return Boolean is + begin + if not Is_One_Dimensional_Array_Type (Atype) then + return False; + end if; + return Is_Psl_Bit_Type (Get_Element_Subtype (Atype)); + end Is_Psl_Bitvector_Type; + + function Sem_Prev_Builtin (Call : Iir; Atype : Iir) return Iir + is + use Vhdl.Sem_Expr; + use Vhdl.Std_Package; + Expr : Iir; + Count : Iir; + Clock : Iir; + First : Boolean; + begin + Expr := Get_Expression (Call); + First := Is_Expr_Not_Analyzed (Expr); + Expr := Sem_Expression_Ov (Expr, Atype); + if Expr /= Null_Iir then + Set_Expression (Call, Expr); + Set_Type (Call, Get_Type (Expr)); + Set_Expr_Staticness (Call, None); + end if; + + if First then + -- Analyze count and clock only once. + Count := Get_Count_Expression (Call); + if Count /= Null_Iir then + Count := Sem_Expression_Wildcard + (Count, Wildcard_Any_Integer_Type); + Count := Eval_Expr (Count); + Set_Count_Expression (Call, Count); + end if; + + Clock := Get_Clock_Expression (Call); + if Clock /= Null_Iir then + Clock := Sem_Expression_Wildcard (Clock, Wildcard_Psl_Bit_Type); + Set_Clock_Expression (Call, Clock); + else + if Current_Psl_Default_Clock = Null_Iir then + Error_Msg_Sem (+Call, "no clock for PSL prev builtin"); + else + Set_Default_Clock (Call, Current_Psl_Default_Clock); + end if; + end if; + end if; + + return Call; + end Sem_Prev_Builtin; + -- Convert VHDL and/or/not nodes to PSL nodes. function Convert_Bool (Expr : Iir) return PSL_Node is diff --git a/src/vhdl/vhdl-sem_psl.ads b/src/vhdl/vhdl-sem_psl.ads index f0f239778..c0f6e85d5 100644 --- a/src/vhdl/vhdl-sem_psl.ads +++ b/src/vhdl/vhdl-sem_psl.ads @@ -19,6 +19,11 @@ with Vhdl.Nodes; use Vhdl.Nodes; package Vhdl.Sem_Psl is + function Is_Psl_Bit_Type (Atype : Iir) return Boolean; + function Is_Psl_Bitvector_Type (Atype : Iir) return Boolean; + + function Sem_Prev_Builtin (Call : Iir; Atype : Iir) return Iir; + procedure Sem_Psl_Declaration (Stmt : Iir); procedure Sem_Psl_Endpoint_Declaration (Stmt : Iir); diff --git a/src/vhdl/vhdl-std_package.adb b/src/vhdl/vhdl-std_package.adb index c5c029a4c..f2ba54382 100644 --- a/src/vhdl/vhdl-std_package.adb +++ b/src/vhdl/vhdl-std_package.adb @@ -108,6 +108,12 @@ package body Vhdl.Std_Package is Wildcard_Any_String_Type); Create_Known_Iir (Iir_Kind_Wildcard_Type_Definition, Wildcard_Any_Access_Type); + Create_Known_Iir (Iir_Kind_Wildcard_Type_Definition, + Wildcard_Any_Integer_Type); + Create_Known_Iir (Iir_Kind_Wildcard_Type_Definition, + Wildcard_Psl_Bit_Type); + Create_Known_Iir (Iir_Kind_Wildcard_Type_Definition, + Wildcard_Psl_Bitvector_Type); end Create_First_Nodes; procedure Create_Std_Standard_Package (Parent : Iir_Library_Declaration) diff --git a/src/vhdl/vhdl-std_package.ads b/src/vhdl/vhdl-std_package.ads index fa94db10a..c066e919f 100644 --- a/src/vhdl/vhdl-std_package.ads +++ b/src/vhdl/vhdl-std_package.ads @@ -174,14 +174,17 @@ package Vhdl.Std_Package is -- Wilcard types. -- Err, we break privacy for iir numbers, but this allow use of them in -- case statements. - Wildcard_Any_Type : constant Iir := 7; + Wildcard_Any_Type : constant Iir := 7; Wildcard_Any_Aggregate_Type : constant Iir := 8; - Wildcard_Any_String_Type : constant Iir := 9; - Wildcard_Any_Access_Type : constant Iir := 10; + Wildcard_Any_String_Type : constant Iir := 9; + Wildcard_Any_Access_Type : constant Iir := 10; + Wildcard_Any_Integer_Type : constant Iir := 11; + Wildcard_Psl_Bit_Type : constant Iir := 12; + Wildcard_Psl_Bitvector_Type : constant Iir := 13; -- Subtype for all wildcard types, so that missing choice can be detected -- at compilation time. - subtype Iir_Wildcard_Types is Iir range 7 .. 10; + subtype Iir_Wildcard_Types is Iir range 7 .. 13; -- Chain of wildcard declarations, to own the nodes. Wildcard_Type_Declaration_Chain : Iir; |