diff options
| -rw-r--r-- | pyGHDL/dom/Sequential.py | 53 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 8 | ||||
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 12 |
3 files changed, 61 insertions, 12 deletions
diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index b0f1d2e97..d2efef8eb 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -51,6 +51,7 @@ from pyVHDLModel.SyntaxModel import ( SequentialProcedureCall as VHDLModel_SequentialProcedureCall, SequentialAssertStatement as VHDLModel_SequentialAssertStatement, SequentialReportStatement as VHDLModel_SequentialReportStatement, + WaitStatement as VHDLModel_WaitStatement, Name, SequentialStatement, Expression, @@ -476,7 +477,11 @@ class SequentialAssertStatement(VHDLModel_SequentialAssertStatement, DOMMixin): condition = GetExpressionFromNode(nodes.Get_Assertion_Condition(assertNode)) message = GetExpressionFromNode(nodes.Get_Report_Expression(assertNode)) severityNode = nodes.Get_Severity_Expression(assertNode) - severity = None if severityNode is nodes.Null_Iir else GetExpressionFromNode(severityNode) + severity = ( + None + if severityNode is nodes.Null_Iir + else GetExpressionFromNode(severityNode) + ) return cls(assertNode, condition, message, severity, label) @@ -499,6 +504,50 @@ class SequentialReportStatement(VHDLModel_SequentialReportStatement, DOMMixin): message = GetExpressionFromNode(nodes.Get_Report_Expression(reportNode)) severityNode = nodes.Get_Severity_Expression(reportNode) - severity = None if severityNode is nodes.Null_Iir else GetExpressionFromNode(severityNode) + severity = ( + None + if severityNode is nodes.Null_Iir + else GetExpressionFromNode(severityNode) + ) return cls(reportNode, message, severity, label) + + +@export +class WaitStatement(VHDLModel_WaitStatement, DOMMixin): + def __init__( + self, + waitNode: Iir, + sensitivityList: Iterable[Name] = None, + condition: Expression = None, + timeout: Expression = None, + label: str = None, + ): + super().__init__(sensitivityList, condition, timeout, label) + DOMMixin.__init__(self, waitNode) + + @classmethod + def parse(cls, waitNode: Iir, label: str) -> "WaitStatement": + from pyGHDL.dom._Utils import GetIirKindOfNode + from pyGHDL.dom._Translate import GetExpressionFromNode + + sensitivityList = None + sensitivityListNode = nodes.Get_Sensitivity_List(waitNode) + if sensitivityListNode is not nodes.Null_Iir: + print(GetIirKindOfNode(sensitivityListNode)) + + conditionNode = nodes.Get_Condition_Clause(waitNode) + condition = ( + None + if conditionNode is nodes.Null_Iir + else GetExpressionFromNode(conditionNode) + ) + + timeoutNode = nodes.Get_Timeout_Clause(waitNode) + timeout = ( + None + if timeoutNode is nodes.Null_Iir + else GetExpressionFromNode(timeoutNode) + ) + + return cls(waitNode, sensitivityList, condition, timeout, label) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 06afa960b..dfc919504 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -40,6 +40,7 @@ from pyGHDL.dom.Sequential import ( CaseStatement, SequentialReportStatement, SequentialAssertStatement, + WaitStatement, ) from pyVHDLModel.SyntaxModel import ( Constraint, @@ -877,7 +878,6 @@ def GetSequentialStatementsFromChainedNodes( label = name_table.Get_Name_Ptr(label) if label != nodes.Null_Iir else None pos = Position.parse(statement) - kind = GetIirKindOfNode(statement) if kind == nodes.Iir_Kind.If_Statement: yield IfStatement.parse(statement, label) @@ -901,11 +901,7 @@ def GetSequentialStatementsFromChainedNodes( ) ) elif kind == nodes.Iir_Kind.Wait_Statement: - print( - "[NOT IMPLEMENTED] For-loop statement (label: '{label}') at line {line}".format( - label=label, line=pos.Line - ) - ) + yield WaitStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Procedure_Call_Statement: print( "[NOT IMPLEMENTED] Procedure call (label: '{label}') at line {line}".format( diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 69f324f37..1f802af47 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -121,10 +121,14 @@ begin when others => end case; - report "hello" & " " & "world"; - report "vhdl" severity note; - assert true nor false report "nothing"; - assert true nor false report "nothing" severity warning; + wait; + wait on a, b; + wait until rising_edge(clock); + wait on clock until rising_edge(clock); + wait for 10 ns; + wait on c for 50 ns; + wait until rising_edge(clock) for 100 ns; + wait on sel until rising_edge(clock) for 100 ns; end process; a <= b; |