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-rw-r--r--testsuite/synth/external01/external01.vhdl58
-rwxr-xr-xtestsuite/synth/external01/testsuite.sh10
2 files changed, 68 insertions, 0 deletions
diff --git a/testsuite/synth/external01/external01.vhdl b/testsuite/synth/external01/external01.vhdl
new file mode 100644
index 000000000..fd4b183f8
--- /dev/null
+++ b/testsuite/synth/external01/external01.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity external01_sub is
+ port (clk : std_logic;
+ rst : std_logic;
+ a : std_logic_vector(7 downto 0);
+ o : out std_logic_vector(7 downto 0));
+end external01_sub;
+
+architecture behav of external01_sub is
+ signal accum : std_logic_vector(7 downto 0);
+begin
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ accum <= (others => '0');
+ else
+ accum <= std_logic_vector(unsigned(accum) + unsigned(a));
+ end if;
+ end if;
+ end process;
+
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ o <= (others => '0');
+ else
+ o <= accum;
+ end if;
+ end if;
+ end process;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity external01 is
+ port (clk : std_logic;
+ rst : std_logic;
+ a : std_logic_vector(7 downto 0);
+ accum : out std_logic_vector(7 downto 0);
+ o : out std_logic_vector(7 downto 0));
+end external01;
+
+architecture behav of external01 is
+begin
+ dut : entity work.external01_sub
+ port map (clk => clk,
+ rst => rst,
+ a => a,
+ o => o);
+ accum <= << signal .external01.dut.accum : std_logic_vector(7 downto 0) >>;
+end behav;
diff --git a/testsuite/synth/external01/testsuite.sh b/testsuite/synth/external01/testsuite.sh
new file mode 100755
index 000000000..964831634
--- /dev/null
+++ b/testsuite/synth/external01/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+GHDL_SYNTH_FLAGS=--keep-hierarchy=no
+
+synth_only external01
+
+echo "Test successful"