diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 414 | ||||
| -rw-r--r-- | src/synth/synth-environment.ads | 2 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 29 | ||||
| -rw-r--r-- | src/synth/synth-expr.ads | 6 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 68 | ||||
| -rw-r--r-- | src/synth/synth-static_oper.adb | 50 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 44 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 5 |
8 files changed, 412 insertions, 206 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index ce31bcf20..5ec9e04f1 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1178,211 +1178,215 @@ class Iir_Predefined: Ieee_1164_Falling_Edge = 195 Ieee_1164_Vector_And_Reduce = 196 Ieee_1164_Vector_Or_Reduce = 197 - Ieee_1164_Condition_Operator = 198 - Ieee_Numeric_Std_Toint_Uns_Nat = 199 - Ieee_Numeric_Std_Toint_Sgn_Int = 200 - Ieee_Numeric_Std_Touns_Nat_Nat_Uns = 201 - Ieee_Numeric_Std_Touns_Nat_Uns_Uns = 202 - Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn = 203 - Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn = 204 - Ieee_Numeric_Std_Resize_Uns_Nat = 205 - Ieee_Numeric_Std_Resize_Sgn_Nat = 206 - Ieee_Numeric_Std_Resize_Uns_Uns = 207 - Ieee_Numeric_Std_Resize_Sgn_Sgn = 208 - Ieee_Numeric_Std_Add_Uns_Uns = 209 - Ieee_Numeric_Std_Add_Uns_Nat = 210 - Ieee_Numeric_Std_Add_Nat_Uns = 211 - Ieee_Numeric_Std_Add_Uns_Log = 212 - Ieee_Numeric_Std_Add_Log_Uns = 213 - Ieee_Numeric_Std_Add_Sgn_Sgn = 214 - Ieee_Numeric_Std_Add_Sgn_Int = 215 - Ieee_Numeric_Std_Add_Int_Sgn = 216 - Ieee_Numeric_Std_Add_Sgn_Log = 217 - Ieee_Numeric_Std_Add_Log_Sgn = 218 - Ieee_Numeric_Std_Sub_Uns_Uns = 219 - Ieee_Numeric_Std_Sub_Uns_Nat = 220 - Ieee_Numeric_Std_Sub_Nat_Uns = 221 - Ieee_Numeric_Std_Sub_Uns_Log = 222 - Ieee_Numeric_Std_Sub_Log_Uns = 223 - Ieee_Numeric_Std_Sub_Sgn_Sgn = 224 - Ieee_Numeric_Std_Sub_Sgn_Int = 225 - Ieee_Numeric_Std_Sub_Int_Sgn = 226 - Ieee_Numeric_Std_Sub_Sgn_Log = 227 - Ieee_Numeric_Std_Sub_Log_Sgn = 228 - Ieee_Numeric_Std_Mul_Uns_Uns = 229 - Ieee_Numeric_Std_Mul_Uns_Nat = 230 - Ieee_Numeric_Std_Mul_Nat_Uns = 231 - Ieee_Numeric_Std_Mul_Sgn_Sgn = 232 - Ieee_Numeric_Std_Mul_Sgn_Int = 233 - Ieee_Numeric_Std_Mul_Int_Sgn = 234 - Ieee_Numeric_Std_Div_Uns_Uns = 235 - Ieee_Numeric_Std_Div_Uns_Nat = 236 - Ieee_Numeric_Std_Div_Nat_Uns = 237 - Ieee_Numeric_Std_Div_Sgn_Sgn = 238 - Ieee_Numeric_Std_Div_Sgn_Int = 239 - Ieee_Numeric_Std_Div_Int_Sgn = 240 - Ieee_Numeric_Std_Gt_Uns_Uns = 241 - Ieee_Numeric_Std_Gt_Uns_Nat = 242 - Ieee_Numeric_Std_Gt_Nat_Uns = 243 - Ieee_Numeric_Std_Gt_Sgn_Sgn = 244 - Ieee_Numeric_Std_Gt_Sgn_Int = 245 - Ieee_Numeric_Std_Gt_Int_Sgn = 246 - Ieee_Numeric_Std_Lt_Uns_Uns = 247 - Ieee_Numeric_Std_Lt_Uns_Nat = 248 - Ieee_Numeric_Std_Lt_Nat_Uns = 249 - Ieee_Numeric_Std_Lt_Sgn_Sgn = 250 - Ieee_Numeric_Std_Lt_Sgn_Int = 251 - Ieee_Numeric_Std_Lt_Int_Sgn = 252 - Ieee_Numeric_Std_Le_Uns_Uns = 253 - Ieee_Numeric_Std_Le_Uns_Nat = 254 - Ieee_Numeric_Std_Le_Nat_Uns = 255 - Ieee_Numeric_Std_Le_Sgn_Sgn = 256 - Ieee_Numeric_Std_Le_Sgn_Int = 257 - Ieee_Numeric_Std_Le_Int_Sgn = 258 - Ieee_Numeric_Std_Ge_Uns_Uns = 259 - Ieee_Numeric_Std_Ge_Uns_Nat = 260 - Ieee_Numeric_Std_Ge_Nat_Uns = 261 - Ieee_Numeric_Std_Ge_Sgn_Sgn = 262 - Ieee_Numeric_Std_Ge_Sgn_Int = 263 - Ieee_Numeric_Std_Ge_Int_Sgn = 264 - Ieee_Numeric_Std_Eq_Uns_Uns = 265 - Ieee_Numeric_Std_Eq_Uns_Nat = 266 - Ieee_Numeric_Std_Eq_Nat_Uns = 267 - Ieee_Numeric_Std_Eq_Sgn_Sgn = 268 - Ieee_Numeric_Std_Eq_Sgn_Int = 269 - Ieee_Numeric_Std_Eq_Int_Sgn = 270 - Ieee_Numeric_Std_Ne_Uns_Uns = 271 - Ieee_Numeric_Std_Ne_Uns_Nat = 272 - Ieee_Numeric_Std_Ne_Nat_Uns = 273 - Ieee_Numeric_Std_Ne_Sgn_Sgn = 274 - Ieee_Numeric_Std_Ne_Sgn_Int = 275 - Ieee_Numeric_Std_Ne_Int_Sgn = 276 - Ieee_Numeric_Std_Match_Gt_Uns_Uns = 277 - Ieee_Numeric_Std_Match_Gt_Uns_Nat = 278 - Ieee_Numeric_Std_Match_Gt_Nat_Uns = 279 - Ieee_Numeric_Std_Match_Gt_Sgn_Sgn = 280 - Ieee_Numeric_Std_Match_Gt_Sgn_Int = 281 - Ieee_Numeric_Std_Match_Gt_Int_Sgn = 282 - Ieee_Numeric_Std_Match_Lt_Uns_Uns = 283 - Ieee_Numeric_Std_Match_Lt_Uns_Nat = 284 - Ieee_Numeric_Std_Match_Lt_Nat_Uns = 285 - Ieee_Numeric_Std_Match_Lt_Sgn_Sgn = 286 - Ieee_Numeric_Std_Match_Lt_Sgn_Int = 287 - Ieee_Numeric_Std_Match_Lt_Int_Sgn = 288 - Ieee_Numeric_Std_Match_Le_Uns_Uns = 289 - Ieee_Numeric_Std_Match_Le_Uns_Nat = 290 - Ieee_Numeric_Std_Match_Le_Nat_Uns = 291 - Ieee_Numeric_Std_Match_Le_Sgn_Sgn = 292 - Ieee_Numeric_Std_Match_Le_Sgn_Int = 293 - Ieee_Numeric_Std_Match_Le_Int_Sgn = 294 - Ieee_Numeric_Std_Match_Ge_Uns_Uns = 295 - Ieee_Numeric_Std_Match_Ge_Uns_Nat = 296 - Ieee_Numeric_Std_Match_Ge_Nat_Uns = 297 - Ieee_Numeric_Std_Match_Ge_Sgn_Sgn = 298 - Ieee_Numeric_Std_Match_Ge_Sgn_Int = 299 - Ieee_Numeric_Std_Match_Ge_Int_Sgn = 300 - Ieee_Numeric_Std_Match_Eq_Uns_Uns = 301 - Ieee_Numeric_Std_Match_Eq_Uns_Nat = 302 - Ieee_Numeric_Std_Match_Eq_Nat_Uns = 303 - Ieee_Numeric_Std_Match_Eq_Sgn_Sgn = 304 - Ieee_Numeric_Std_Match_Eq_Sgn_Int = 305 - Ieee_Numeric_Std_Match_Eq_Int_Sgn = 306 - Ieee_Numeric_Std_Match_Ne_Uns_Uns = 307 - Ieee_Numeric_Std_Match_Ne_Uns_Nat = 308 - Ieee_Numeric_Std_Match_Ne_Nat_Uns = 309 - Ieee_Numeric_Std_Match_Ne_Sgn_Sgn = 310 - Ieee_Numeric_Std_Match_Ne_Sgn_Int = 311 - Ieee_Numeric_Std_Match_Ne_Int_Sgn = 312 - Ieee_Numeric_Std_Shl_Uns_Nat = 313 - Ieee_Numeric_Std_Shr_Uns_Nat = 314 - Ieee_Numeric_Std_Shl_Sgn_Nat = 315 - Ieee_Numeric_Std_Shr_Sgn_Nat = 316 - Ieee_Numeric_Std_Sll_Uns_Int = 317 - Ieee_Numeric_Std_Sll_Sgn_Int = 318 - Ieee_Numeric_Std_Srl_Uns_Int = 319 - Ieee_Numeric_Std_Srl_Sgn_Int = 320 - Ieee_Numeric_Std_Sla_Uns_Int = 321 - Ieee_Numeric_Std_Sla_Sgn_Int = 322 - Ieee_Numeric_Std_Sra_Uns_Int = 323 - Ieee_Numeric_Std_Sra_Sgn_Int = 324 - Ieee_Numeric_Std_Rol_Uns_Nat = 325 - Ieee_Numeric_Std_Ror_Uns_Nat = 326 - Ieee_Numeric_Std_Rol_Sgn_Nat = 327 - Ieee_Numeric_Std_Ror_Sgn_Nat = 328 - Ieee_Numeric_Std_Not_Uns = 329 - Ieee_Numeric_Std_Not_Sgn = 330 - Ieee_Numeric_Std_Abs_Sgn = 331 - Ieee_Numeric_Std_And_Uns_Uns = 332 - Ieee_Numeric_Std_And_Sgn_Sgn = 333 - Ieee_Numeric_Std_Or_Uns_Uns = 334 - Ieee_Numeric_Std_Or_Sgn_Sgn = 335 - Ieee_Numeric_Std_Nand_Uns_Uns = 336 - Ieee_Numeric_Std_Nand_Sgn_Sgn = 337 - Ieee_Numeric_Std_Nor_Uns_Uns = 338 - Ieee_Numeric_Std_Nor_Sgn_Sgn = 339 - Ieee_Numeric_Std_Xor_Uns_Uns = 340 - Ieee_Numeric_Std_Xor_Sgn_Sgn = 341 - Ieee_Numeric_Std_Xnor_Uns_Uns = 342 - Ieee_Numeric_Std_Xnor_Sgn_Sgn = 343 - Ieee_Numeric_Std_Neg_Uns = 344 - Ieee_Numeric_Std_Neg_Sgn = 345 - Ieee_Numeric_Std_Match_Log = 346 - Ieee_Numeric_Std_Match_Uns = 347 - Ieee_Numeric_Std_Match_Sgn = 348 - Ieee_Numeric_Std_Match_Slv = 349 - Ieee_Numeric_Std_Match_Suv = 350 - Ieee_Math_Real_Ceil = 351 - Ieee_Math_Real_Round = 352 - Ieee_Math_Real_Log2 = 353 - Ieee_Math_Real_Sin = 354 - Ieee_Math_Real_Cos = 355 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 356 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 357 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 358 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 359 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 360 - Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 361 - Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 362 - Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 363 - Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 364 - Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 365 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 366 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 367 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 368 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 369 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 370 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 371 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 372 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 373 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 374 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 375 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 376 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 377 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 378 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 379 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 380 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 381 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 382 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 383 - Ieee_Std_Logic_Unsigned_Conv_Integer = 384 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 385 - Ieee_Std_Logic_Signed_Add_Slv_Int = 386 - Ieee_Std_Logic_Signed_Add_Int_Slv = 387 - Ieee_Std_Logic_Signed_Add_Slv_Sl = 388 - Ieee_Std_Logic_Signed_Add_Sl_Slv = 389 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 390 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 391 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 392 - Ieee_Std_Logic_Signed_Sub_Slv_Sl = 393 - Ieee_Std_Logic_Signed_Sub_Sl_Slv = 394 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 395 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 396 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 397 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 398 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 399 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 400 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 401 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 402 + Ieee_1164_Vector_Sll = 198 + Ieee_1164_Vector_Srl = 199 + Ieee_1164_Vector_Rol = 200 + Ieee_1164_Vector_Ror = 201 + Ieee_1164_Condition_Operator = 202 + Ieee_Numeric_Std_Toint_Uns_Nat = 203 + Ieee_Numeric_Std_Toint_Sgn_Int = 204 + Ieee_Numeric_Std_Touns_Nat_Nat_Uns = 205 + Ieee_Numeric_Std_Touns_Nat_Uns_Uns = 206 + Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn = 207 + Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn = 208 + Ieee_Numeric_Std_Resize_Uns_Nat = 209 + Ieee_Numeric_Std_Resize_Sgn_Nat = 210 + Ieee_Numeric_Std_Resize_Uns_Uns = 211 + Ieee_Numeric_Std_Resize_Sgn_Sgn = 212 + Ieee_Numeric_Std_Add_Uns_Uns = 213 + Ieee_Numeric_Std_Add_Uns_Nat = 214 + Ieee_Numeric_Std_Add_Nat_Uns = 215 + Ieee_Numeric_Std_Add_Uns_Log = 216 + Ieee_Numeric_Std_Add_Log_Uns = 217 + Ieee_Numeric_Std_Add_Sgn_Sgn = 218 + Ieee_Numeric_Std_Add_Sgn_Int = 219 + Ieee_Numeric_Std_Add_Int_Sgn = 220 + Ieee_Numeric_Std_Add_Sgn_Log = 221 + Ieee_Numeric_Std_Add_Log_Sgn = 222 + Ieee_Numeric_Std_Sub_Uns_Uns = 223 + Ieee_Numeric_Std_Sub_Uns_Nat = 224 + Ieee_Numeric_Std_Sub_Nat_Uns = 225 + Ieee_Numeric_Std_Sub_Uns_Log = 226 + Ieee_Numeric_Std_Sub_Log_Uns = 227 + Ieee_Numeric_Std_Sub_Sgn_Sgn = 228 + Ieee_Numeric_Std_Sub_Sgn_Int = 229 + Ieee_Numeric_Std_Sub_Int_Sgn = 230 + Ieee_Numeric_Std_Sub_Sgn_Log = 231 + Ieee_Numeric_Std_Sub_Log_Sgn = 232 + Ieee_Numeric_Std_Mul_Uns_Uns = 233 + Ieee_Numeric_Std_Mul_Uns_Nat = 234 + Ieee_Numeric_Std_Mul_Nat_Uns = 235 + Ieee_Numeric_Std_Mul_Sgn_Sgn = 236 + Ieee_Numeric_Std_Mul_Sgn_Int = 237 + Ieee_Numeric_Std_Mul_Int_Sgn = 238 + Ieee_Numeric_Std_Div_Uns_Uns = 239 + Ieee_Numeric_Std_Div_Uns_Nat = 240 + Ieee_Numeric_Std_Div_Nat_Uns = 241 + Ieee_Numeric_Std_Div_Sgn_Sgn = 242 + Ieee_Numeric_Std_Div_Sgn_Int = 243 + Ieee_Numeric_Std_Div_Int_Sgn = 244 + Ieee_Numeric_Std_Gt_Uns_Uns = 245 + Ieee_Numeric_Std_Gt_Uns_Nat = 246 + Ieee_Numeric_Std_Gt_Nat_Uns = 247 + Ieee_Numeric_Std_Gt_Sgn_Sgn = 248 + Ieee_Numeric_Std_Gt_Sgn_Int = 249 + Ieee_Numeric_Std_Gt_Int_Sgn = 250 + Ieee_Numeric_Std_Lt_Uns_Uns = 251 + Ieee_Numeric_Std_Lt_Uns_Nat = 252 + Ieee_Numeric_Std_Lt_Nat_Uns = 253 + Ieee_Numeric_Std_Lt_Sgn_Sgn = 254 + Ieee_Numeric_Std_Lt_Sgn_Int = 255 + Ieee_Numeric_Std_Lt_Int_Sgn = 256 + Ieee_Numeric_Std_Le_Uns_Uns = 257 + Ieee_Numeric_Std_Le_Uns_Nat = 258 + Ieee_Numeric_Std_Le_Nat_Uns = 259 + Ieee_Numeric_Std_Le_Sgn_Sgn = 260 + Ieee_Numeric_Std_Le_Sgn_Int = 261 + Ieee_Numeric_Std_Le_Int_Sgn = 262 + Ieee_Numeric_Std_Ge_Uns_Uns = 263 + Ieee_Numeric_Std_Ge_Uns_Nat = 264 + Ieee_Numeric_Std_Ge_Nat_Uns = 265 + Ieee_Numeric_Std_Ge_Sgn_Sgn = 266 + Ieee_Numeric_Std_Ge_Sgn_Int = 267 + Ieee_Numeric_Std_Ge_Int_Sgn = 268 + Ieee_Numeric_Std_Eq_Uns_Uns = 269 + Ieee_Numeric_Std_Eq_Uns_Nat = 270 + Ieee_Numeric_Std_Eq_Nat_Uns = 271 + Ieee_Numeric_Std_Eq_Sgn_Sgn = 272 + Ieee_Numeric_Std_Eq_Sgn_Int = 273 + Ieee_Numeric_Std_Eq_Int_Sgn = 274 + Ieee_Numeric_Std_Ne_Uns_Uns = 275 + Ieee_Numeric_Std_Ne_Uns_Nat = 276 + Ieee_Numeric_Std_Ne_Nat_Uns = 277 + Ieee_Numeric_Std_Ne_Sgn_Sgn = 278 + Ieee_Numeric_Std_Ne_Sgn_Int = 279 + Ieee_Numeric_Std_Ne_Int_Sgn = 280 + Ieee_Numeric_Std_Match_Gt_Uns_Uns = 281 + Ieee_Numeric_Std_Match_Gt_Uns_Nat = 282 + Ieee_Numeric_Std_Match_Gt_Nat_Uns = 283 + Ieee_Numeric_Std_Match_Gt_Sgn_Sgn = 284 + Ieee_Numeric_Std_Match_Gt_Sgn_Int = 285 + Ieee_Numeric_Std_Match_Gt_Int_Sgn = 286 + Ieee_Numeric_Std_Match_Lt_Uns_Uns = 287 + Ieee_Numeric_Std_Match_Lt_Uns_Nat = 288 + Ieee_Numeric_Std_Match_Lt_Nat_Uns = 289 + Ieee_Numeric_Std_Match_Lt_Sgn_Sgn = 290 + Ieee_Numeric_Std_Match_Lt_Sgn_Int = 291 + Ieee_Numeric_Std_Match_Lt_Int_Sgn = 292 + Ieee_Numeric_Std_Match_Le_Uns_Uns = 293 + Ieee_Numeric_Std_Match_Le_Uns_Nat = 294 + Ieee_Numeric_Std_Match_Le_Nat_Uns = 295 + Ieee_Numeric_Std_Match_Le_Sgn_Sgn = 296 + Ieee_Numeric_Std_Match_Le_Sgn_Int = 297 + Ieee_Numeric_Std_Match_Le_Int_Sgn = 298 + Ieee_Numeric_Std_Match_Ge_Uns_Uns = 299 + Ieee_Numeric_Std_Match_Ge_Uns_Nat = 300 + Ieee_Numeric_Std_Match_Ge_Nat_Uns = 301 + Ieee_Numeric_Std_Match_Ge_Sgn_Sgn = 302 + Ieee_Numeric_Std_Match_Ge_Sgn_Int = 303 + Ieee_Numeric_Std_Match_Ge_Int_Sgn = 304 + Ieee_Numeric_Std_Match_Eq_Uns_Uns = 305 + Ieee_Numeric_Std_Match_Eq_Uns_Nat = 306 + Ieee_Numeric_Std_Match_Eq_Nat_Uns = 307 + Ieee_Numeric_Std_Match_Eq_Sgn_Sgn = 308 + Ieee_Numeric_Std_Match_Eq_Sgn_Int = 309 + Ieee_Numeric_Std_Match_Eq_Int_Sgn = 310 + Ieee_Numeric_Std_Match_Ne_Uns_Uns = 311 + Ieee_Numeric_Std_Match_Ne_Uns_Nat = 312 + Ieee_Numeric_Std_Match_Ne_Nat_Uns = 313 + Ieee_Numeric_Std_Match_Ne_Sgn_Sgn = 314 + Ieee_Numeric_Std_Match_Ne_Sgn_Int = 315 + Ieee_Numeric_Std_Match_Ne_Int_Sgn = 316 + Ieee_Numeric_Std_Shl_Uns_Nat = 317 + Ieee_Numeric_Std_Shr_Uns_Nat = 318 + Ieee_Numeric_Std_Shl_Sgn_Nat = 319 + Ieee_Numeric_Std_Shr_Sgn_Nat = 320 + Ieee_Numeric_Std_Sll_Uns_Int = 321 + Ieee_Numeric_Std_Sll_Sgn_Int = 322 + Ieee_Numeric_Std_Srl_Uns_Int = 323 + Ieee_Numeric_Std_Srl_Sgn_Int = 324 + Ieee_Numeric_Std_Sla_Uns_Int = 325 + Ieee_Numeric_Std_Sla_Sgn_Int = 326 + Ieee_Numeric_Std_Sra_Uns_Int = 327 + Ieee_Numeric_Std_Sra_Sgn_Int = 328 + Ieee_Numeric_Std_Rol_Uns_Nat = 329 + Ieee_Numeric_Std_Ror_Uns_Nat = 330 + Ieee_Numeric_Std_Rol_Sgn_Nat = 331 + Ieee_Numeric_Std_Ror_Sgn_Nat = 332 + Ieee_Numeric_Std_Not_Uns = 333 + Ieee_Numeric_Std_Not_Sgn = 334 + Ieee_Numeric_Std_Abs_Sgn = 335 + Ieee_Numeric_Std_And_Uns_Uns = 336 + Ieee_Numeric_Std_And_Sgn_Sgn = 337 + Ieee_Numeric_Std_Or_Uns_Uns = 338 + Ieee_Numeric_Std_Or_Sgn_Sgn = 339 + Ieee_Numeric_Std_Nand_Uns_Uns = 340 + Ieee_Numeric_Std_Nand_Sgn_Sgn = 341 + Ieee_Numeric_Std_Nor_Uns_Uns = 342 + Ieee_Numeric_Std_Nor_Sgn_Sgn = 343 + Ieee_Numeric_Std_Xor_Uns_Uns = 344 + Ieee_Numeric_Std_Xor_Sgn_Sgn = 345 + Ieee_Numeric_Std_Xnor_Uns_Uns = 346 + Ieee_Numeric_Std_Xnor_Sgn_Sgn = 347 + Ieee_Numeric_Std_Neg_Uns = 348 + Ieee_Numeric_Std_Neg_Sgn = 349 + Ieee_Numeric_Std_Match_Log = 350 + Ieee_Numeric_Std_Match_Uns = 351 + Ieee_Numeric_Std_Match_Sgn = 352 + Ieee_Numeric_Std_Match_Slv = 353 + Ieee_Numeric_Std_Match_Suv = 354 + Ieee_Math_Real_Ceil = 355 + Ieee_Math_Real_Round = 356 + Ieee_Math_Real_Log2 = 357 + Ieee_Math_Real_Sin = 358 + Ieee_Math_Real_Cos = 359 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 360 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 361 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 362 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 363 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 364 + Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 365 + Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 366 + Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 367 + Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 368 + Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 369 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 370 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 371 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 372 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 373 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 374 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 375 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 376 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 377 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 378 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 379 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 380 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 381 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 382 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 383 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 384 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 385 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 386 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 387 + Ieee_Std_Logic_Unsigned_Conv_Integer = 388 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 389 + Ieee_Std_Logic_Signed_Add_Slv_Int = 390 + Ieee_Std_Logic_Signed_Add_Int_Slv = 391 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 392 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 393 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 394 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 395 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 396 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 397 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 398 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 399 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 400 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 401 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 402 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 403 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 404 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 405 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 406 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/synth/synth-environment.ads b/src/synth/synth-environment.ads index 1f4b24711..acf97c45f 100644 --- a/src/synth/synth-environment.ads +++ b/src/synth/synth-environment.ads @@ -85,6 +85,7 @@ package Synth.Environment is -- The current value of WID. For variables, this is the last assigned -- value. For signals, this is the initial value. + -- A builder is needed in case of concatenation. function Get_Current_Value (Ctxt : Builders.Context_Acc; Wid : Wire_Id) return Net; @@ -92,7 +93,6 @@ package Synth.Environment is (Ctxt : Builders.Context_Acc; Wid : Wire_Id; Off : Uns32; Wd : Width) return Net; - -- Read and write the mark flag. function Get_Wire_Mark (Wid : Wire_Id) return Boolean; procedure Set_Wire_Mark (Wid : Wire_Id; Mark : Boolean := True); diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 8e334cc2a..15d0d622d 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -68,6 +68,35 @@ package body Synth.Expr is return Get_Net_Int64 (N); end Get_Static_Discrete; + function Is_Positive (V : Value_Acc) return Boolean + is + N : Net; + Inst : Instance; + begin + pragma Assert (V.Typ.Kind = Type_Discrete); + case V.Kind is + when Value_Discrete => + return V.Scal >= 0; + when Value_Const => + return V.C_Val.Scal >= 0; + when Value_Net => + N := V.N; + when Value_Wire => + N := Get_Net (V); + when others => + raise Internal_Error; + end case; + Inst := Get_Net_Parent (N); + case Get_Id (Inst) is + when Id_Uextend + | Id_Const_UB32 => + return True; + when others => + -- Be conservative. + return False; + end case; + end Is_Positive; + procedure From_Std_Logic (Enum : Int64; Val : out Uns32; Zx : out Uns32) is begin case Enum is diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads index 08936a15a..c5969b483 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-expr.ads @@ -38,13 +38,19 @@ package Synth.Expr is Loc : Source.Syn_Src) return Value_Acc; + -- For a static value V, return the value. function Get_Static_Discrete (V : Value_Acc) return Int64; + -- Return True only if discrete value V is known to be positive or 0. + -- False means either not positive or unknown. + function Is_Positive (V : Value_Acc) return Boolean; + -- Return the bounds of a one dimensional array/vector type and the -- width of the element. procedure Get_Onedimensional_Array_Bounds (Typ : Type_Acc; Bnd : out Bound_Type; El_Typ : out Type_Acc); + -- Create an array subtype from bound BND. function Create_Onedimensional_Array_Subtype (Btyp : Type_Acc; Bnd : Bound_Type) return Type_Acc; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index c32099fd3..513eef626 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -34,6 +34,7 @@ with Netlists; use Netlists; with Netlists.Gates; use Netlists.Gates; with Netlists.Builders; use Netlists.Builders; with Netlists.Folds; use Netlists.Folds; +with Netlists.Utils; with Synth.Errors; use Synth.Errors; with Synth.Stmts; use Synth.Stmts; @@ -416,6 +417,64 @@ package body Synth.Oper is Set_Location (N, Expr); return Create_Value_Net (N, Res_Typ); end Synth_Compare_Sgn_Sgn; + + function Synth_Shift (Id_Pos : Module_Id; Id_Neg : Module_Id) + return Value_Acc + is + pragma Unreferenced (Id_Neg); + L1, R1 : Net; + N : Net; + Is_Pos : Boolean; + begin + Is_Pos := Is_Positive (Right); + + L1 := Get_Net (Left); + R1 := Get_Net (Right); + if Is_Pos then + N := Build_Shift_Rotate (Ctxt, Id_Pos, L1, R1); + else + raise Internal_Error; + end if; + Set_Location (N, Expr); + return Create_Value_Net (N, Create_Res_Bound (Left)); + end Synth_Shift; + + function Synth_Rotation (Id : Module_Id) return Value_Acc + is + Amt : Int64; + Ww : Width; + L1, R1 : Net; + N : Net; + begin + if Is_Static_Val (Right) then + Amt := Get_Static_Discrete (Right); + if Amt < 0 then + raise Internal_Error; + end if; + Amt := Amt mod Int64 (Left.Typ.W); + R1 := Build_Const_UB32 (Ctxt, Uns32 (Amt), Right.Typ.W); + Set_Location (R1, Right_Expr); + elsif not Is_Positive (Right) then + Error_Msg_Synth (+Expr, "rotation quantity must be unsigned"); + return Left; + else + R1 := Get_Net (Right); + Ww := Netlists.Utils.Clog2 (Left.Typ.W); + if Right.Typ.W >= Ww then + if Mutils.Is_Power2 (Uns64 (Left.Typ.W)) then + R1 := Build2_Trunc (Ctxt, Id_Utrunc, R1, Ww, +Expr); + else + Error_Msg_Synth + (+Expr, "vector length of rotation must be a power of 2"); + return Left; + end if; + end if; + end if; + L1 := Get_Net (Left); + N := Build_Shift_Rotate (Ctxt, Id, L1, R1); + Set_Location (N, Expr); + return Create_Value_Net (N, Create_Res_Bound (Left)); + end Synth_Rotation; begin Left := Synth_Expression_With_Type (Syn_Inst, Left_Expr, Left_Typ); Left := Synth_Subtype_Conversion (Left, Left_Typ, False, Expr); @@ -951,6 +1010,15 @@ package body Synth.Oper is Error_Msg_Synth (+Expr, "non-constant division not supported"); return null; + when Iir_Predefined_Ieee_Numeric_Std_Sra_Sgn_Int => + return Synth_Shift (Id_Asr, Id_None); + + when Iir_Predefined_Ieee_Numeric_Std_Sll_Uns_Int => + return Synth_Shift (Id_Lsl, Id_None); + + when Iir_Predefined_Ieee_1164_Vector_Ror => + return Synth_Rotation (Id_Ror); + when others => Error_Msg_Synth (+Expr, "synth_dyadic_operation: unhandled " & Iir_Predefined_Functions'Image (Def)); diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 15a41a9dc..6db92757c 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -260,6 +260,44 @@ package body Synth.Static_Oper is end; end Synth_Mul_Sgn_Sgn; + function Synth_Shift (Val : Value_Acc; + Amt : Uns32; + Right : Boolean; + Arith : Boolean) return Value_Acc + is + Len : constant Uns32 := Uns32 (Val.Arr.Len); + Arr : Std_Logic_Vector (1 .. Natural (Len)); + Pad : Std_Ulogic; + begin + if Len = 0 or Amt >= Len then + Arr := (others => '0'); + else + To_Std_Logic_Vector (Val, Arr); + if Arith then + Pad := Arr (1); + else + Pad := '0'; + end if; + + if Right then + for I in reverse Amt + 1 .. Len loop + Arr (Natural (I)) := Arr (Natural (I - Amt)); + end loop; + for I in 1 .. Amt loop + Arr (Natural (I)) := Pad; + end loop; + else + for I in 1 .. Len - Amt loop + Arr (Natural (I)) := Arr (Natural (I + Amt)); + end loop; + for I in Len - Amt + 1 .. Len loop + Arr (Natural (I)) := Pad; + end loop; + end if; + end if; + return To_Value_Acc (Arr, Val.Typ.Vec_El); + end Synth_Shift; + function Synth_Static_Dyadic_Predefined (Syn_Inst : Synth_Instance_Acc; Imp : Node; Left : Value_Acc; @@ -467,6 +505,18 @@ package body Synth.Static_Oper is when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn => return Synth_Mul_Sgn_Sgn (Left, Right, Expr); + when Iir_Predefined_Ieee_Numeric_Std_Srl_Uns_Int => + declare + Amt : Int64; + begin + Amt := Get_Static_Discrete (Right); + if Amt >= 0 then + return Synth_Shift (Left, Uns32 (Amt), True, False); + else + return Synth_Shift (Left, Uns32 (-Amt), False, False); + end if; + end; + when others => Error_Msg_Synth (+Expr, "synth_static_dyadic_predefined: unhandled " diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 9c123d16a..be78f6afc 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -19,6 +19,7 @@ with Types; use Types; with Name_Table; with Std_Names; use Std_Names; with Vhdl.Errors; use Vhdl.Errors; +with Vhdl.Std_Package; package body Vhdl.Ieee.Std_Logic_1164 is function Is_Scalar_Parameter (Inter : Iir) return Boolean is @@ -34,6 +35,12 @@ package body Vhdl.Ieee.Std_Logic_1164 is or Base_Type = Std_Logic_Vector_Type; end Is_Vector_Parameter; + function Is_Integer_Parameter (Inter : Iir) return Boolean is + begin + return (Get_Base_Type (Get_Type (Inter)) + = Std_Package.Integer_Type_Definition); + end Is_Integer_Parameter; + -- Return True iff the profile of FUNC is: (l, r : std_ulogic) function Is_Scalar_Scalar_Function (Func : Iir) return Boolean is @@ -98,6 +105,30 @@ package body Vhdl.Ieee.Std_Logic_1164 is return True; end Is_Vector_Vector_Function; + -- Return True iff the profile of FUNC is: + -- (l : std_[u]logic_vector; r : integer) + function Is_Vector_Integer_Function (Func : Iir) return Boolean + is + Inter : constant Iir := Get_Interface_Declaration_Chain (Func); + Inter2 : Iir; + begin + if Get_Implicit_Definition (Func) /= Iir_Predefined_None then + return False; + end if; + if Inter = Null_Iir or else not Is_Vector_Parameter (Inter) then + return False; + end if; + Inter2 := Get_Chain (Inter); + if Inter2 = Null_Iir or else not Is_Integer_Parameter (Inter2) then + return False; + end if; + if Get_Chain (Inter2) /= Null_Iir then + return False; + end if; + + return True; + end Is_Vector_Integer_Function; + -- Return True iff the profile of FUNC is: (l : std_[u]logic_vector) function Is_Vector_Function (Func : Iir) return Boolean is @@ -310,6 +341,19 @@ package body Vhdl.Ieee.Std_Logic_1164 is when others => Predefined := Iir_Predefined_None; end case; + elsif Is_Vector_Integer_Function (Decl) then + case Get_Identifier (Decl) is + when Name_Sll => + Predefined := Iir_Predefined_Ieee_1164_Vector_Sll; + when Name_Srl => + Predefined := Iir_Predefined_Ieee_1164_Vector_Srl; + when Name_Rol => + Predefined := Iir_Predefined_Ieee_1164_Vector_Rol; + when Name_Ror => + Predefined := Iir_Predefined_Ieee_1164_Vector_Ror; + when others => + Predefined := Iir_Predefined_None; + end case; else Predefined := Iir_Predefined_None; end if; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index c7bec2747..44618964c 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5456,6 +5456,11 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Vector_And_Reduce, Iir_Predefined_Ieee_1164_Vector_Or_Reduce, + Iir_Predefined_Ieee_1164_Vector_Sll, + Iir_Predefined_Ieee_1164_Vector_Srl, + Iir_Predefined_Ieee_1164_Vector_Rol, + Iir_Predefined_Ieee_1164_Vector_Ror, + Iir_Predefined_Ieee_1164_Condition_Operator, -- Numeric_Std. |