diff options
| -rw-r--r-- | doc/appendix/Meta.rst | 26 | ||||
| -rw-r--r-- | doc/appendix/Roadmap.rst | 13 | ||||
| -rw-r--r-- | doc/building/Building.rst | 6 | ||||
| -rw-r--r-- | doc/building/Directories.rst | 22 | ||||
| -rw-r--r-- | doc/building/PrecompileVendorPrimitives.rst | 140 | ||||
| -rw-r--r-- | doc/building/gcc/GNULinux-GNAT.rst | 14 | ||||
| -rw-r--r-- | doc/building/gcc/index.rst | 2 | ||||
| -rw-r--r-- | doc/building/llvm/GNULinux-GNAT.rst | 2 | ||||
| -rw-r--r-- | doc/building/llvm/Windows-MinGW-GNAT.rst | 4 | ||||
| -rw-r--r-- | doc/building/mcode/GNULinux-GNAT.rst | 4 | ||||
| -rw-r--r-- | doc/building/mcode/Windows-MinGW-GNAT.rst | 4 | ||||
| -rw-r--r-- | doc/building/mcode/index.rst | 4 | ||||
| -rw-r--r-- | doc/contribute.rst | 30 | ||||
| -rw-r--r-- | doc/getting/Releases.rst | 6 | ||||
| -rw-r--r-- | doc/licenses.rst | 12 | ||||
| -rw-r--r-- | doc/references/CodingStyle.rst | 26 | ||||
| -rw-r--r-- | doc/references/CommandReference.rst | 32 | ||||
| -rw-r--r-- | doc/references/ImplementationOfVHDL.rst | 170 | ||||
| -rw-r--r-- | doc/references/ImplementationOfVITAL.rst | 42 | ||||
| -rw-r--r-- | doc/using/InvokingGHDL.rst | 225 | ||||
| -rw-r--r-- | doc/using/QuickStartGuide.rst | 198 | ||||
| -rw-r--r-- | doc/using/Simulation.rst | 116 |
22 files changed, 544 insertions, 554 deletions
diff --git a/doc/appendix/Meta.rst b/doc/appendix/Meta.rst index e549c6a96..5a95f1793 100644 --- a/doc/appendix/Meta.rst +++ b/doc/appendix/Meta.rst @@ -6,10 +6,10 @@ Meta General guidelines to edit the documentation ******************************************** - 1) It’s better for version control systems and diff tools to break lines at a sensible number of characters. Long lines appear as one diff. Also merging is more complex because merges are line based. Long unbreakable items may be longer (links, refs, …). We chose to use 160 chars. + 1) It’s better for version control systems and diff tools to break lines at a sensible number of characters. Long lines appear as one diff. Also merging is more complex because merges are line based. Long unbreakable items may be longer (links, refs, etc.). We chose to use 160 chars. 2) Please indent all directive content by 3 spaces (not 2, and no tabs). - 3) Please use ``*`` as an itemize character, since ``-`` and ``+`` are supported by docutils, but not officially supported by Sphinx`. - 4) Please underline all headlines with at least as many characters as the headline is long. Following the Python pattern for headline the levels are: + 3) Please use ``*`` as an itemize character, since ``-`` and ``+`` are supported by docutils, but not officially supported by Sphinx. + 4) Please underline all headlines with at least as many characters as the headline is long. Following the Python pattern for headlines the levels are: .. code:: @@ -29,7 +29,7 @@ General guidelines to edit the documentation .. code:: - ``…`` + ``code`` is samp. ``:samp:`` is only required when you want to write italic text in code text. @@ -39,13 +39,13 @@ General guidelines to edit the documentation Now, variable becomes italic. - Please simplify all usages of :samp:`…`to ``…`` for readability. Here are the regular expressions for an editor like Notepad++: + Please simplify all usages of ``:samp:`code``` to ````code```` for readability. Here are the regular expressions for an editor like Notepad++: - Search pattern:: :samp:`(.+?)` - Replace pattern:: ``\1`` - 6) Each backend has one folder and each platform/compiler has one file. Please note that page headlines are different from ToC headline: + 6) Each backend has one folder and each platform/compiler has one file. Please note that page headlines are different from ToC headlines: .. code:: @@ -55,24 +55,24 @@ General guidelines to edit the documentation ToC entry <file1> file2 - 7) A documentation should not use “you”, “we”, …, because it’s not an interactive conversation or informal letter. It’s like a thesis, everything is structured and formal. However, to make it more friendly to newcomers, we agree to allow informal language in section ':ref:`USING:QuickStart`'. + 7) Documentation should not use “you”, “we”, …, because it’s not an interactive conversation or informal letter. It’s like a thesis, everything is structured and formal. However, to make it more friendly to newcomers, we agree to allow informal language in the section :ref:`USING:QuickStart`. - 8) Please keep errors low. + 8) Please keep errors to a minimum. Guidelines to edit section 'Building' ************************************* -I prefer a text block, which explains how a compilation works, what I can configure for that backend, etc. After that, I prefer a code block with e.g. bash instructions on how to compile a backend. A list of instructions with embedded bash lines is not helpful. An experienced, as well as novice user, would like to copy a set of instructions into the shell. But it should be stated what these instructions will do. Complex flows like for GCC, can be split into multiple shell code blocks. Moreover, I find it essential, to demonstrate when and where to change directories. +We prefer a text block, which explains how a compilation works, what we can configure for that backend, etc. After that, we prefer a code block with e.g. bash instructions on how to compile a backend. A list of instructions with embedded bash lines is not helpful. An experienced, as well as novice user, would like to copy a set of instructions into the shell. But it should be stated what these instructions will do. Complex flows like for GCC, can be split into multiple shell code blocks. Moreover, we find it essential to demonstrate when and where to change directories. -We would like to see a list like +We would like to see a list like: * gcc (Gnu Compiler Collection) * gcc-gnat (Ada compiler for GCC) * llvm-del (LLVM development package) * ... -The goal is to also explain what a user is installing and what the few lines in the build description do. Now they know the name, can search for similar names if the have another package manager or distro or can ask Google/Wikipedia. We often find many build receipts with cryptic shell code and to execute this unknown stuff with sudo is not comfortable. We would like to know what it does before hiting enter. +The goal is also to explain what a user is installing and what the few lines in the build description do. Now they know the name, can search for similar names if they have another package manager or distro or can ask Google/Wikipedia. We often find many build receipts with cryptic shell code and to execute this unknown stuff with sudo is not comfortable. We would like to know what it does before hitting enter. Documentation configuration *************************** @@ -97,7 +97,7 @@ Documentation configuration CSS *** -* The indentation of the elements in the side menu have been modified. They are fixed por levels 1, 2 and 3 (`#294 <https://github.com/ghdl/ghdl/pull/294#issuecomment-281555760>`_) and 4 (later). +* The indentation of the elements in the side menu have been modified. They are fixed for levels 1, 2 and 3 (`#294 <https://github.com/ghdl/ghdl/pull/294#issuecomment-281555760>`_) and 4 (later). * The RTD menu (bottom-left) has been modified (`#294 <https://github.com/ghdl/ghdl/pull/294#issuecomment-281513494>`_): @@ -107,4 +107,4 @@ CSS Dist **** -* Ubuntu uses `dash` instead of `bash` when a shell script is run. As a result, some functionalities, such as arrays like ``array[1]``, are not supported. Therefore, build scripts in `dist/linux` should not use those functionalities unless they are sourced in a `bash` shell. That is, :file:`tavis-ci.sh` uses arrays, since it is sourced in the Travis CI machine. But :file:`docker-buildtest.sh` and :file:`buildtest.sh` do not use any. The same applies to the scripts in `testsuite`.
\ No newline at end of file +* Ubuntu uses `dash` instead of `bash` when a shell script is run. As a result, some functionalities, such as arrays like ``array[1]``, are not supported. Therefore, build scripts in `dist/linux` should not use those functionalities unless they are sourced in a `bash` shell. That is, :file:`travis-ci.sh` uses arrays, since it is sourced in the Travis CI machine. But :file:`docker-buildtest.sh` and :file:`buildtest.sh` do not use any. The same applies to the scripts in `testsuite`.
\ No newline at end of file diff --git a/doc/appendix/Roadmap.rst b/doc/appendix/Roadmap.rst index 7854e3b68..19f673e81 100644 --- a/doc/appendix/Roadmap.rst +++ b/doc/appendix/Roadmap.rst @@ -3,14 +3,13 @@ Roadmap | Future Improvements ############################# -I have several axes for `GHDL` improvements: +We have several axes for `GHDL` improvements: -* Documentation. -* Better diagnostics messages (warning and error). -* Full support of VHDL-2008. -* Optimization (simulation speed). +* Documentation +* Better diagnostics messages (warning and error) +* Full support of VHDL-2008 +* Optimization (simulation speed) * Graphical tools (to see waves and to debug) * Style checks * VITAL acceleration - -.. todolist:: + diff --git a/doc/building/Building.rst b/doc/building/Building.rst index 0add10fe3..5cc5bd29d 100644 --- a/doc/building/Building.rst +++ b/doc/building/Building.rst @@ -51,14 +51,14 @@ Here is a short comparison, so that you can choose the one you want to use: be replaced with direct execution of the binary. See section :ref:`USING:QuickStart`. After making your choice, you can jump to the corresponding section. -However, we suggest you to read :ref:`BUILD:dir_structure` before, so that you -know where the content is placed and which temporal files are expected to be +However, we suggest you to read :ref:`BUILD:dir_structure` first, so that you +know where the content will be placed and which files are expected to be created. .. HINT:: Since GHDL is written in `Ada`, independently of the code generator you use, the `GNU Ada compiler`, `GNAT GPL`, is required, 2014 (or later) for ``x86`` - (32 or 64 bits). `GNAT GPL` can be downloaded anonymously from `libre.adacore.com <http://libre.adacore.com/tools/gnat-gpl-edition/>`_. + (32 or 64 bit). `GNAT GPL` can be downloaded anonymously from `libre.adacore.com <http://libre.adacore.com/tools/gnat-gpl-edition/>`_. Then, untar and run the doinstall script. Alternatively, most GNU/Linux provide a package named ``gcc-ada`` or ``gcc-gnat``. diff --git a/doc/building/Directories.rst b/doc/building/Directories.rst index 94fcf49d5..6b3c105f0 100644 --- a/doc/building/Directories.rst +++ b/doc/building/Directories.rst @@ -6,21 +6,21 @@ Directory Structure * ``src``: sources of GHDL, all of them in Ada. * ``libraries``: mostly third party libraries such as, `ieee`, `mentor`, - `std`, `synopsys` and `vital`. Except a few shell and `Python` scripts, all + `std`, `synopsys` and `vital`. Except for a few shell and `Python` scripts, all the content is written in VHDL. * Vendors like Altera, Lattice and Xilinx have their own simulation libraries, - especially for FPGA primitives, soft and hard macros. These libraries can - not be shipped with GHDL, but we offer prepared compile scripts to + especially for FPGA primitives, soft and hard macros. These libraries cannot + be shipped with GHDL, but we offer prepared compile scripts to pre-compile the vendor libraries, if the vendor tool is present on the computer. These are located in ``libraries/vendor``. See :ref:`GETTING:PrecompVendor` for information on how to use them. -* ``dist``: scripts and auxiliar files to build GHDL in different +* ``dist``: scripts and auxiliary files to build GHDL in different environments: - * ``gcc``: header and configuration files to build GHDL with GCC (all the + * ``gcc``: header and configuration files to build GHDL with GCC (all platforms). * ``linux``: build and test script written in shell, and other auxiliary files used to i) launch docker containers and ii) automate multiple builds @@ -32,19 +32,19 @@ Directory Structure * ``appveyor``: * ``doc``: `Markdown` and `reStructuredText` sources and auxiliary files to - build the documentation with `Sphinx <http://www.sphinx-doc.org>`_. Indeed, - `Read the docs <http://readthedocs.org>`_ (RTD) is used to automatically build + build the documentation with `Sphinx <http://www.sphinx-doc.org>`_. In fact, + `Read the Docs <http://readthedocs.org>`_ (RTD) is used to automatically build and deploy this site and/or PDF you are reading. -* ``testsuite``: see section :ref:`test_suites`. +* ``testsuite``: files used for testing. * `.yml` configuration files for CI environments (``readthedocs``, - ``travis`` and ``appveyor``) and `ignore` files for source control + ``travis``, and ``appveyor``) and `ignore` files for source control management tools (``git`` and ``.hg``). * Files for building GHDL: ``configure`` and ``Makefile.in``. -* Auxiliar files for development: ``.gdbinit`` and ``ghdl.gpr.in`` +* Auxiliary files for development: ``.gdbinit`` and ``ghdl.gpr.in`` (GNAT project file). -* Text files: ``COPYING.md``, ``NEWS.md`` and ``README.md``. +* Text files: ``COPYING.md``, ``NEWS.md``, and ``README.md``. diff --git a/doc/building/PrecompileVendorPrimitives.rst b/doc/building/PrecompileVendorPrimitives.rst index 1a3171a2d..714dc053d 100644 --- a/doc/building/PrecompileVendorPrimitives.rst +++ b/doc/building/PrecompileVendorPrimitives.rst @@ -4,7 +4,7 @@ Precompile Vendor Primitives ############################ Vendors like Altera, Lattice and Xilinx have their own simulation libraries, -especially for FPGA primitives, soft and hard macros. These libraries can not +especially for FPGA primitives, soft and hard macros. These libraries cannot be shipped with *GHDL*, but we offer prepared compile scripts to pre-compile the vendor libraries, if the vendor tool is present on the computer. There are also popular simulation and verification libraries like OSVVM [#f1]_ or @@ -29,7 +29,7 @@ Supported Vendors Libraries * `stratixiv`, `stratixiv_pcie_hip` * `stratixv`, `stratixv_pcie_hip` * `fiftyfivenm`, `twentynm` - + * Lattice (3.6 or later): * `ec` @@ -56,8 +56,8 @@ Supported Simulation and Verification Libraries * OSVVM (for VHDL-2008) - * osvvm - + * osvvm + * UVVM (for VHDL-2008) * uvvm-utilities @@ -77,9 +77,9 @@ Script Configuration ==================== The vendor library compile scripts need to know where the used / latest vendor -tool chain is installed. Therefore, the script implement a default installation -directory search as well as environment variable checks. If a vendor tool could -not be detected or the script choses the wrong vendor library source directory, +tool chain is installed. Therefore, the scripts implement a default installation +directory search as well as environment variable checks. If a vendor tool cannot +be detected or the script chooses the wrong vendor library source directory, then it's possible to provide the path via `--source` or `-Source`. The generated output is stored relative to the current working directory. The @@ -91,7 +91,7 @@ To compile all source files with GHDL, the simulator executable is searched in environment variable `GHDL` or by passing the parameter `--ghdl` or `-GHDL` to the scripts. -If the vendor library compilation is used very often, we recommend to configure +If the vendor library compilation is used very often, we recommend configuring these parameters in `config.sh` or `config.psm1`, so the command line can be shortened to the essential parts. @@ -101,7 +101,7 @@ Compiling on Linux ================== * **Step 0 - Configure the scripts (optional)** - See next section for how to configure `config.sh`. + See the next section for how to configure `config.sh`. * **Step 1 - Browse to your simulation working directory** @@ -149,8 +149,7 @@ Compiling on Windows ==================== * **Step 0 - Configure the scripts (optional)** - - See next section for how to configure `config.psm1`. + See the next section for how to configure `config.psm1`. * **Step 1 - Browse to your simulation working directory** @@ -170,8 +169,8 @@ Compiling on Windows PS> <GHDL>\libraries\vendors\compile-uvvm.ps1 -All * **Step 3 - Viewing the result** - This creates vendor directories in your current working directory and - compiles the vendor files into them. + This creates vendor directories in your current working directory and + compiles the vendor files into them. .. code-block:: PowerShell @@ -197,7 +196,7 @@ For Linux: `config.sh` ---------------------- Please open the `config.sh` file and set the dictionary entries for the -installed vendor tools to the appropriate directory to your tool's installation +installed vendor tools to your tool's installation directories. Use an empty string `""` for not installed tools. `config.sh`: @@ -217,7 +216,7 @@ For Windows: `config.psm1` -------------------------- Please open the `config.psm1` file and set the dictionary entries for the -installed vendor tools to the appropriate directory to your tool's installation +installed vendor tools to your tool's installation folder. Use an empty string `""` for not installed tools. `config.psm1`: @@ -237,95 +236,92 @@ folder. Use an empty string `""` for not installed tools. Selectable Options for the Bash Scripts: ---------------------------------------- -*First I should translate the scripts before writing the docu...* - * Common parameters to most scripts: - .. code-block:: raw - - -h --help Print the embedded help page(s). - -c --clean Cleanup directory before analyzing. - -n --no-warnings Don't show warnings. Report errors only. - -s --skip-existing Skip already compiled files (an *.o file exists). - -S --skip-largefiles Don't compile large entities like DSP and PCIe primitives. - -H --halt-on-error Stop compiling if an error occurred. + .. code-block:: none + + --help, -h Print the embedded help page(s). + --clean, -c Cleanup directory before analyzing. + --no-warnings, -n Don't show warnings. Report errors only. + --skip-existing, -s Skip already compiled files (an *.o file exists). + --skip-largefiles, -S Don't compile large entities like DSP and PCIe primitives. + --halt-on-error, -H Stop compiling if an error occurred. * `compile-altera.sh` Selectable libraries: - .. code-block:: raw + .. code-block:: none - -a --all Compile all libraries, including common libraries, packages and device libraries. - --altera Compile base libraries like 'altera' and 'altera_mf' - --max Compile device libraries for Max CPLDs - --arria Compile device libraries for Arria FPGAs - --cyclone Compile device libraries for Cyclone FPGAs - --stratix Compile device libraries for Stratix FPGAs + --all, -a Compile all libraries, including common libraries, packages and device libraries. + --altera Compile base libraries like 'altera' and 'altera_mf' + --max Compile device libraries for Max CPLDs + --arria Compile device libraries for Arria FPGAs + --cyclone Compile device libraries for Cyclone FPGAs + --stratix Compile device libraries for Stratix FPGAs - Compile options: + Compile options: - .. code-block:: raw + .. code-block:: none - - --vhdl93 Compile selected libraries with VHDL-93 (default). - --vhdl2008 Compile selected libraries with VHDL-2008. + --vhdl93 Compile selected libraries with VHDL-93 (default). + --vhdl2008 Compile selected libraries with VHDL-2008. * `compile-xilinx-ise.sh` Selectable libraries: - .. code-block:: raw + .. code-block:: none - -a --all Compile all libraries, including common libraries, packages and device libraries. - --unisim Compile the unisim primitives - --unimacro Compile the unimacro macros - --simprim Compile the simprim primitives - --corelib Compile the xilinxcorelib macros - --secureip Compile the secureip primitives + --all, -a Compile all libraries, including common libraries, packages and device libraries. + --unisim Compile the unisim primitives + --unimacro Compile the unimacro macros + --simprim Compile the simprim primitives + --corelib Compile the xilinxcorelib macros + --secureip Compile the secureip primitives Compile options: - .. code-block:: raw + .. code-block:: none - --vhdl93 Compile selected libraries with VHDL-93 (default). - --vhdl2008 Compile selected libraries with VHDL-2008. + --vhdl93 Compile selected libraries with VHDL-93 (default). + --vhdl2008 Compile selected libraries with VHDL-2008. * `compile-xilinx-vivado.sh` Selectable libraries: - .. code-block:: raw + .. code-block:: none - -a --all Compile all libraries, including common libraries, packages and device libraries. - --unisim Compile the unisim primitives - --unimacro Compile the unimacro macros - --secureip Compile the secureip primitives + --all, -a Compile all libraries, including common libraries, packages and device libraries. + --unisim Compile the unisim primitives + --unimacro Compile the unimacro macros + --secureip Compile the secureip primitives Compile options: - .. code-block:: raw + .. code-block:: none - --vhdl93 Compile selected libraries with VHDL-93 (default). - --vhdl2008 Compile selected libraries with VHDL-2008. + --vhdl93 Compile selected libraries with VHDL-93 (default). + --vhdl2008 Compile selected libraries with VHDL-2008. * `compile-osvvm.sh` Selectable libraries: - .. code-block:: raw + .. code-block:: none - -a --all Compile all. - --osvvm Compile the OSVVM library. + --all, -a Compile all. + --osvvm Compile the OSVVM library. * `compile-uvvm.sh` Selectable libraries: - .. code-block:: raw + .. code-block:: none - -a --all Compile all. - --uvvm Compile the UVVM libraries. + --all, -a Compile all. + --uvvm Compile the UVVM libraries. Selectable Options for the PowerShell Scripts: @@ -333,7 +329,7 @@ Selectable Options for the PowerShell Scripts: * Common parameters to all scripts: - .. code-block:: raw + .. code-block:: none -Help Print the embedded help page(s). -Clean Cleanup directory before analyzing. @@ -343,7 +339,7 @@ Selectable Options for the PowerShell Scripts: Selectable libraries: - .. code-block:: raw + .. code-block:: none -All Compile all libraries, including common libraries, packages and device libraries. -Altera Compile base libraries like 'altera' and 'altera_mf' @@ -354,7 +350,7 @@ Selectable Options for the PowerShell Scripts: Compile options: - .. code-block:: raw + .. code-block:: none -VHDL93 Compile selected libraries with VHDL-93 (default). -VHDL2008 Compile selected libraries with VHDL-2008. @@ -363,7 +359,7 @@ Selectable Options for the PowerShell Scripts: Selectable libraries: - .. code-block:: raw + .. code-block:: none -All Compile all libraries, including common libraries, packages and device libraries. -Unisim Compile the unisim primitives @@ -374,7 +370,7 @@ Selectable Options for the PowerShell Scripts: Compile options: - .. code-block:: raw + .. code-block:: none -VHDL93 Compile selected libraries with VHDL-93 (default). -VHDL2008 Compile selected libraries with VHDL-2008. @@ -383,7 +379,7 @@ Selectable Options for the PowerShell Scripts: Selectable libraries: - .. code-block:: raw + .. code-block:: none -All Compile all libraries, including common libraries, packages and device libraries. -Unisim Compile the unisim primitives @@ -392,7 +388,7 @@ Selectable Options for the PowerShell Scripts: Compile options: - .. code-block:: raw + .. code-block:: none -VHDL93 Compile selected libraries with VHDL-93 (default). -VHDL2008 Compile selected libraries with VHDL-2008. @@ -401,19 +397,19 @@ Selectable Options for the PowerShell Scripts: Selectable libraries: - .. code-block:: raw + .. code-block:: none -All Compile all. - -OSVVM Compile the OSVVM library. + -OSVVM Compile the OSVVM library. * `compile-uvvm.ps1` Selectable libraries: - .. code-block:: raw + .. code-block:: none -All Compile all. - -UVVM Compile the UVVM libraries. + -UVVM Compile the UVVM libraries. -------------------------------------------------------------------------------- diff --git a/doc/building/gcc/GNULinux-GNAT.rst b/doc/building/gcc/GNULinux-GNAT.rst index 632c2a5e8..f58e3b2ef 100644 --- a/doc/building/gcc/GNULinux-GNAT.rst +++ b/doc/building/gcc/GNULinux-GNAT.rst @@ -3,17 +3,13 @@ GCC Backend on GNU/Linux with GCC/GNAT ###################################### -.. HINT:: There are some dependencies for building GCC (``gmp``, ``mpfr`` and ``mpc``). If you have not them installed on your system, you can either build them manually or use the ``download_prerequisites`` script provided in the GCC source tree (recommended): ``cd /path/to/gcc/source/dir && ./contrib/download_prerequisites``. +.. HINT:: There are some dependencies for building GCC (``gmp``, ``mpfr`` and ``mpc``). If you have not installed them on your system, you can either build them manually or use the ``download_prerequisites`` script provided in the GCC source tree (recommended): ``cd /path/to/gcc/source/dir && ./contrib/download_prerequisites``. -* First configure GHDL, specify GCC source directory and installation prefix - (like ``/usr/local`` or ``/opt/ghdl``). +* First configure GHDL, specify GCC source directory and installation prefix (like ``/usr/local`` or ``/opt/ghdl``). -* Next, invoke ``make copy-sources`` to copy GHDL sources in the source - directory. +* Next, invoke ``make copy-sources`` to copy GHDL sources in the source directory. -* Then, configure GCC. The list of ``--disable`` configure options can be - adjusted to your needs. GHDL does not require all these optional libraries - and disabling them will speed-up the build. +* Then, configure GCC. The list of ``--disable`` configure options can be adjusted to your needs. GHDL does not require all these optional libraries and disabling them will speed up the build. * Now, build and install GCC with ``make``. @@ -37,7 +33,7 @@ GCC Backend on GNU/Linux with GCC/GNAT $ make ghdllib $ make install -.. HINT:: Note that the prefix directory to configure ``gcc`` must be the same as the one used to configure GHDL. If you have manually built ``gmp``/``mpfr``/``mpc`` (without using the script in ``contrib``) and if you have installed them in a non-standard directory, you may need to add ``--with-gmp=GMP_INSTALL_DIR``. +.. HINT:: Note that the prefix directory to configure ``gcc`` must be the same as the one used to configure GHDL. If you have manually built ``gmp``/``mpfr``/``mpc`` (without using the script in ``contrib``), and, if you have installed them in a non-standard directory, you may need to add ``--with-gmp=GMP_INSTALL_DIR``. .. HINT:: If your system gcc was configured with ``--enable-default-pie`` (check if that option appears in the output of ``gcc -v``), you should also add it. diff --git a/doc/building/gcc/index.rst b/doc/building/gcc/index.rst index 5d76e1684..f3d1a3123 100644 --- a/doc/building/gcc/index.rst +++ b/doc/building/gcc/index.rst @@ -33,7 +33,7 @@ GCC Backend AGCC_GCCSRC_DIR=/path/to/gcc/sources AGCC_GCCOBJ_DIR=/path/to/gcc/build -.. HINT :: For ppc64 (and AIX ?) platform, the object file format contains an identifier for the source language. Because gcc doesn't know about the VHDL, gcc crashes very early. This could be fixed with a very simple change in ``gcc/config/rs6000/rs6000.c``, ``function rs6000_output_function_epilogue`` (as of gcc 4.8): +.. HINT :: For ppc64 (and AIX ?) platform, the object file format contains an identifier for the source language. Because gcc doesn't know about VHDL, gcc crashes very early. This could be fixed with a very simple change in ``gcc/config/rs6000/rs6000.c``, ``function rs6000_output_function_epilogue`` (as of gcc 4.8): .. CODE:: C diff --git a/doc/building/llvm/GNULinux-GNAT.rst b/doc/building/llvm/GNULinux-GNAT.rst index 5f97c99b7..e8a66d425 100644 --- a/doc/building/llvm/GNULinux-GNAT.rst +++ b/doc/building/llvm/GNULinux-GNAT.rst @@ -3,7 +3,7 @@ LLVM Backend on GNU/Linux with GCC/GNAT ####################################### -.. HINT:: You need to install LLVM (usually depends on ``libedit``, see :ghdlsharp:`29`). The supported versions are 3.5 till 5.0, but debugging is only supported with LLVM 3.5. +.. HINT:: You need to install LLVM (usually depends on ``libedit``, see :ghdlsharp:`29`). The supported versions are 3.5 til 5.0, but debugging is only supported with LLVM 3.5. * First configure GHDL with the proper arg ``./configure --with-llvm-config``. If ``llvm-config`` is not in your path, you can specify it: ``./configure --with-llvm-config=LLVM_INSTALL/bin/llvm-config``. diff --git a/doc/building/llvm/Windows-MinGW-GNAT.rst b/doc/building/llvm/Windows-MinGW-GNAT.rst index 0fce8f068..59d70023f 100644 --- a/doc/building/llvm/Windows-MinGW-GNAT.rst +++ b/doc/building/llvm/Windows-MinGW-GNAT.rst @@ -3,11 +3,11 @@ LLVM Backend on Windows with GCC/GNAT (MinGW) ############################################# -On Windows with MinGW, GHDL is configured by ``configure`` and build by ``make``. +On Windows with MinGW, GHDL is configured by ``configure`` and built by ``make``. * First, GHDL needs to be configured. It is common to specify a ``PREFIX`` (installation directory like ``/usr/local`` or ``/opt/ghdl``). Without any - other option, ``configure`` select `mcode` as backend. + other option, ``configure`` selects `mcode` as the backend. * Next, ``make`` starts the compilation process. diff --git a/doc/building/mcode/GNULinux-GNAT.rst b/doc/building/mcode/GNULinux-GNAT.rst index 2c75efa96..2d7598599 100644 --- a/doc/building/mcode/GNULinux-GNAT.rst +++ b/doc/building/mcode/GNULinux-GNAT.rst @@ -3,11 +3,11 @@ mcode Backend on GNU/Linux with GCC/GNAT ######################################## -On Linux, GHDL is configured by ``configure`` and build by ``make``. +On Linux, GHDL is configured by ``configure`` and built by ``make``. * First, GHDL needs to be configured. It is common to specify a ``PREFIX`` (installation directory like ``/usr/local`` or ``/opt/ghdl``). Without any - other option, ``configure`` select `mcode` as backend. + other option, ``configure`` selects `mcode` as the backend. * Next, ``make`` starts the compilation process. diff --git a/doc/building/mcode/Windows-MinGW-GNAT.rst b/doc/building/mcode/Windows-MinGW-GNAT.rst index 960ced421..f1482ccb8 100644 --- a/doc/building/mcode/Windows-MinGW-GNAT.rst +++ b/doc/building/mcode/Windows-MinGW-GNAT.rst @@ -3,11 +3,11 @@ mcode Backend on Windows with GCC/GNAT (MinGW) ############################################## -On Windows with MinGW, GHDL is configured by ``configure`` and build by ``make``. +On Windows with MinGW, GHDL is configured by ``configure`` and built by ``make``. * First, GHDL needs to be configured. It is common to specify a ``PREFIX`` (installation directory like ``/usr/local`` or ``/opt/ghdl``). Without any - other option, ``configure`` select `mcode` as backend. + other option, ``configure`` selects `mcode` as the backend. * Next, ``make`` starts the compilation process. diff --git a/doc/building/mcode/index.rst b/doc/building/mcode/index.rst index 0b081392a..92eeaabd4 100644 --- a/doc/building/mcode/index.rst +++ b/doc/building/mcode/index.rst @@ -3,8 +3,8 @@ mcode Backend ############# -The mcode backend is available for all supported platforms and is also the most -simplest procedure, because it requires the least dependencies and configuration +The mcode backend is available for all supported platforms and is also the +simplest procedure, because it requires the fewest dependencies and configuration options. diff --git a/doc/contribute.rst b/doc/contribute.rst index cf1ca7c2a..ee8bbf0de 100644 --- a/doc/contribute.rst +++ b/doc/contribute.rst @@ -4,16 +4,16 @@ Contributing ############ -The first step might be to use GHDL and explore it's possibilities in an own project. If you are new to VHDL, see the +The first step might be to use GHDL and explore its possibilities in your own project. If you are new to VHDL, see the :ref:`USING:QuickStart` for an introduction. Furthermore, we encourage you to read :ref:`USING:Invoking`, where the most commonly used options are explained. You can also check the complete :ref:`REF:Command`. -If you are more familiar with GHDL, you might start asking yourself how it works internally. Then, you might find +If you are more familiar with GHDL, you might start asking yourself how it works internally. If so, you might find :ref:`Implementation of VHDL <REF:ImplVHDL>` and :ref:`Implementation of VITAL <REF:ImplVITAL>` interesting. -While using GHDL, you might find flaws, such as bugs, missing features, typos in the documentation or topics which are -still not covered. In order to improve GHDL, we welcome bug reports, suggestions and contributions for any aspect of -GHDL. Either if it's a bug or an enhancement, have a look at the |SHIELD:issues-open| and |SHIELD:issues-closed| to see +While using GHDL, you might find flaws, such as bugs, missing features, typos in the documentation, or topics which still are +not covered. In order to improve GHDL, we welcome bug reports, suggestions, and contributions for any aspect of +GHDL. Whether it's a bug or an enhancement, have a look at the |SHIELD:issues-open| and |SHIELD:issues-closed| to see if someone already told us about it. You might find a solution there. If you found no information on your topic, please, report so that we are aware! You can reach us through various ways: @@ -34,31 +34,31 @@ Reporting bugs * If the compiler crashes, this is a bug. Reliable tools never crash. * If the compiler emits an error message for a perfectly valid input or does not emit an error message for an invalid input, this may be a bug. * If the executable created from your VHDL sources crashes, this may be a bug at runtime or the code itself may be wrong. However, since VHDL has a notion of pointers, an erroneous VHDL program (using invalid pointers for example) may crash. - * If a compiler message is not clear enough, please tell us. The error messages can be improved, but we have not enough experience with them. + * If a compiler message is not clear enough, please tell us. The error messages can be improved, but we do not have enough experience with them. Please, report issues of this kind through |SHIELD:bug-report|, as this allows us to categorize issues into groups and -assign developers to them. You can track the issue’s state and see how it’s getting solved. +to assign developers to them. You can track the issue’s state and see how it’s getting solved. .. IMPORTANT:: - To make it easier, please elaborate a `Minimum (non) Working Example` (`MWE <https://en.wikipedia.org/wiki/Minimal_Working_Example>`_) prior to sending the report, so that the possible bug source is isolated. Shall the MWE compile and run, it is a good idea to make it look like a test and make an assert statement should finish the execution; the severity level `note` indicates success, while a severity level `failure` indicates failure. + As suggested in the bug report template, please elaborate a `Minimal (non) Working Example` (`MWE <https://en.wikipedia.org/wiki/Minimal_Working_Example>`_) prior to sending the report, so that the possible bug source is isolated. Should it fulfill the format requirements of `issue-runner <https://github.com/1138-4EB/issue-runner>`_, you would be able to test your bug with the latest GHDL version. Please do so in order to ensure that the bug is not solved already. - Then, please include enough information for the maintainers to reproduce the problem. This includes: + Also, please include enough information in the bug report, for the maintainers to reproduce the problem. The template includes: * Operating system and version of GHDL (you can get it with :samp:`ghdl --version`). - * Whether you have built GHDL from sources (provide short SHA of the used commit) or used the binary distribution (tell which release/tag). + * Whether you have built GHDL from sources (provide short SHA of the used commit) or used the binary distribution (note which release/tag). * If you cannot compile, please report which compiler you are using and the version. - * Content of the input files which make the MWE + * Content of the input files which comprise the MWE * Description of the problem: * Comment explaining whether the MWE should compile or not; if yes, whether or not is should run until the assertion. - * What you expected to happen and what you actually get. If you know the LRM well enough, please specify the paragraph which might be not well implemented. + * What you expect to happen and what you actually get. If you know the LRM well enough, please specify which paragraph might not be implemented well. * Samples of any log. * Anything else that you think would be helpful. .. NOTE:: - If you don't know the LRM, be aware that an issue claimed as bug report may be rejected because there is no bug according to it. GHDL aims at implementing VHDL as defined in `IEEE 1076 <http://ieeexplore.ieee.org/document/4772740/>`_. However, some other tools allow constructs which do not fully follow the standard revisions. Therefore, comparisons with other VHDL is not a solid argument. Some of them are supported by GHDL (see :ref:`IEEE_library_pitfalls`), but any such enhancement will have very low priority. + If you don't know the LRM, be aware that an issue claimed as a bug report may be rejected because there is no bug according to it. GHDL aims at implementing VHDL as defined in `IEEE 1076 <http://ieeexplore.ieee.org/document/4772740/>`_. However, some other tools allow constructs which do not fully follow the standard revisions. Therefore, comparisons with other VHDL is not a solid argument. Some of them are supported by GHDL (see :ref:`IEEE_library_pitfalls`), but any such enhancement will have very low priority. .. _requesting_enhancements: @@ -75,7 +75,7 @@ Improving the documentation If you found a mistake in the documentation, please send a comment. If you didn't understand some parts of this manual, please tell us. English is not our mother tongue, so this documentation may not be well-written. -Likewise, rewriting part of the documentation or missing content (such as, examples) is a good way to improve it. Since +Likewise, rewriting part of the documentation or missing content (such as examples) is a good way to improve it. Since it automatically is built from `reStructuredText` and `Markdown` sources, you can fork, modify and request the maintainers to pull your copy. See :ref:`pull_request`. @@ -94,7 +94,7 @@ write access to our repositories, the project is hosted at GitHub, which follows 1. Make a copy (`fork <https://help.github.com/articles/fork-a-repo/>`_) of the project. 2. Do the changes you wish (edit, add, rename, move and/or delete). -3. When you think that the changes are ready to be merged, you notify the maintainers by opening a `Pull Request <https://help.github.com/articles/creating-a-pull-request/>`_ (PR). +3. When you think that the changes are ready to be merged, notify the maintainers by opening a `Pull Request <https://help.github.com/articles/creating-a-pull-request/>`_ (PR). 4. The maintainers will review the proposed changes and will reply in the corresponding thread if any further modification is required. If so, you can keep adding commits to the same branch, and the PR will be automatically updated. 5. Last, the maintainers will merge your branch. You will be notified, the PR will be closed, and you'll be allowed to delete the branch, if you want. diff --git a/doc/getting/Releases.rst b/doc/getting/Releases.rst index 9a2d896e0..4dba31e92 100644 --- a/doc/getting/Releases.rst +++ b/doc/getting/Releases.rst @@ -151,9 +151,9 @@ On Windows All Windows command line instructions are intended for :program:`Windows PowerShell`, if not marked otherwise. So executing the following instructions in Windows - Command Prompt (:program:`cmd.exe`) won't function or result in errors! See - the :ref:`Requirements section <GETTING:Require>` on where to - download or update PowerShell. + Command Prompt (:program:`cmd.exe`) won't function or will result in errors! + :program:`Windows PowerShell` can be installed or upgraded to v5.1 by installing the + `Windows Management Framework <https://docs.microsoft.com/en-us/powershell/wmf/5.1/install-configure>`_. Command line instructions to clone GHDL onto a Windows machine with HTTPS protocol: diff --git a/doc/licenses.rst b/doc/licenses.rst index 106325dde..120a273b1 100644 --- a/doc/licenses.rst +++ b/doc/licenses.rst @@ -4,7 +4,7 @@ Copyrights | Licenses ##################### -- The GHDL front-end, package :samp:`std.textio` and the runtime library, :samp:`grt`, are given under :ref:`LIC:GPLv2`. +- The GHDL front-end package :samp:`std.textio`, and the runtime library :samp:`grt` are given under :ref:`LIC:GPLv2`. - The documentation is given under :ref:`LIC:CC-BY-SA`. .. WARNING:: @@ -41,9 +41,9 @@ CC-BY-SA This is a free documentation; you can redistribute it and/or modify it under the terms of the `Creative Commons Attribution-ShareAlike 4.0 <https://creativecommons.org/licenses/by-sa/4.0/>`_ license. You are free to **share** (copy and redistribute the material in any medium or format) and/or **adapt** (remix, transform, and build upon the material for any purpose, even commercially). We cannot revoke these freedoms as long as you follow the these terms: -- **Attribution**: you must provide the name of the creator and attribution parties (`more info <https://wiki.creativecommons.org/wiki/License_Versions#Detailed_attribution_comparison_chart>`_), a copyright notice, a license notice, a disclaimer notice, a link to the material, a link to the license and indicate if changes were made (see `marking guide <https://wiki.creativecommons.org/wiki/Best_practices_for_attribution#This_is_a_good_attribution_for_material_you_modified_slightly>`_ and `more info <https://wiki.creativecommons.org/wiki/License_Versions#Modifications_and_adaptations_must_be_marked_as_such>`_ ). You may do so in any reasonable manner, but not in any way that suggests we endorses you or your use. +- **Attribution**: you must provide the name of the creator and attribution parties (`more info <https://wiki.creativecommons.org/wiki/License_Versions#Detailed_attribution_comparison_chart>`_), a copyright notice, a license notice, a disclaimer notice, a link to the material, a link to the license and indicate if changes were made (see `marking guide <https://wiki.creativecommons.org/wiki/Best_practices_for_attribution#This_is_a_good_attribution_for_material_you_modified_slightly>`_ and `more info <https://wiki.creativecommons.org/wiki/License_Versions#Modifications_and_adaptations_must_be_marked_as_such>`_). You may do so in any reasonable manner, but not in any way that suggests we endorse you or your use. - **ShareAlike**: if you remix, transform, or build upon the material, you must distribute your contributions under the same license as the original. -- No additional restrictions: you may not apply legal terms or technological measures that legally restrict others from doing anything the license permits. +- **No additional restrictions**: you may not apply legal terms or technological measures that legally restrict others from doing anything the license permits. See `CC-BY-SA-4.0 Legal Code <https://creativecommons.org/licenses/by-sa/4.0/legalcode.txt>`_ for more details. @@ -70,7 +70,7 @@ van Rantwijk, Joris Debian packaging Only those who made substantial contributions are shown in the table above, but many others contributed with minor patches. You can find a list at |SHIELD:contributors| -With apologies to anyone who ought to be either on this table or in the GitHub contributor list, but isn't. Thanks also to all those who have reported bugs and support issues, and often patches and testcases to either the late gna! website or `sourceforge.net/p/ghdl-updates/tickets <https://sourceforge.net/p/ghdl-updates/tickets/>`_ . +With apologies to anyone who ought to be either on this table or in the GitHub contributor list, but isn't. Thanks also to all those who have reported bugs and support issues, and often patches and testcases to either the late gna! website or `sourceforge.net/p/ghdl-updates/tickets <https://sourceforge.net/p/ghdl-updates/tickets/>`_. -------------------------------------------------------------------------------- @@ -78,5 +78,5 @@ With apologies to anyone who ought to be either on this table or in the GitHub c .. rubric:: Footnotes - .. [#f1] In alphabetical order. - .. [#f2] Maintainer. + .. [#f1] In alphabetical order + .. [#f2] Maintainer diff --git a/doc/references/CodingStyle.rst b/doc/references/CodingStyle.rst index 3c9b9f398..6af869067 100644 --- a/doc/references/CodingStyle.rst +++ b/doc/references/CodingStyle.rst @@ -4,17 +4,17 @@ Coding Style ############ Ada subset: use only a simple (VHDL like) subset of Ada: no tasking, no -controlled types... VHDL users should easily understand that subset. +controlled types... VHDL users should easily understand that subset. Allowed Ada95 features: the standard library, child packages. Use assertions. We try to follow the 'GNU Coding Standards' when possible: comments before -declarations, two spaces at end of sentences, finish sentences with a dot. -But: 3 spaces for indentation. +declarations, one space at the end of sentences, finish sentences with a dot. +But: 2 spaces for indentation in code blocks. -No trailing spaces, not TAB (HT). +No trailing spaces, no TAB (HT). -Subprograms must have a comment before to describe it, like: +Subprograms must have a comment before to describe them, like: .. code-block:: Ada @@ -22,7 +22,7 @@ Subprograms must have a comment before to describe it, like: procedure Sem_Concurrent_Statement_Chain (Parent : Iir); The line before the comment must be a blank line (unless this is the first -declaration). Don't repeat the comment before the subprogram body. +declaration). Don't repeat the comment before the subprogram body. * For subprograms: @@ -74,15 +74,15 @@ declaration). Don't repeat the comment before the subprogram body. Loc : Iir) return O_Enode - 7) If not possible, ask yourself what is wrong! Shorten a name. + 7. If not possible, ask yourself what is wrong! Shorten a name. -* Rule for the 'is': one a new line only if the declarative part is not empty: +* Rule for the 'is': on a new line only if the declarative part is not empty: .. code-block:: Ada procedure Translate_Assign (Target : Mnode; Expr : Iir; Target_Type : Iir) is - Val : O_Enode; + Val : O_Enode; begin vs. @@ -92,7 +92,7 @@ declaration). Don't repeat the comment before the subprogram body. function Translate_Static_Range_Dir (Expr : Iir) return O_Cnode is begin - If the parametere line is too long with the 'is', put in on a separate line: + If the parameter line is too long with the 'is', put in on a separate line: .. code-block:: Ada @@ -130,9 +130,9 @@ declaration). Don't repeat the comment before the subprogram body. .. code-block:: Ada is - N_Info : constant Iir := Get_Sub_Aggregate_Info (Info); - Assoc : Iir; - Sub : Iir; + N_Info : constant Iir := Get_Sub_Aggregate_Info (Info); + Assoc : Iir; + Sub : Iir; begin If the initialization expression has a side effect (such as allocation), do diff --git a/doc/references/CommandReference.rst b/doc/references/CommandReference.rst index 16430cb72..de6ff5415 100644 --- a/doc/references/CommandReference.rst +++ b/doc/references/CommandReference.rst @@ -24,8 +24,8 @@ Help [``-h``] .. option:: --help, -h Display (on the standard output) a short description of the all the commands -available. If the help switch is followed by a command switch, then options -for this later command are displayed:: +available. If the help switch is followed by a command switch, then options +for that second command are displayed:: ghdl --help ghdl -h @@ -57,7 +57,7 @@ Version [``--version``] .. option:: --version, -v -Display the GHDL version and exit. +Display the GHDL version. File commands ============= @@ -72,7 +72,7 @@ Pretty print [``--pp-html``] .. option:: --pp-html <[options] file...> -The files are just scanned and an html file, with syntax highlighting is generated on standard output. Since the files are not even parsed, erroneous files or incomplete designs can be pretty printed. +The files are just scanned and an html file with syntax highlighting is generated on standard output. Since the files are not even parsed, erroneous files or incomplete designs can be pretty printed. The style of the html file can be modified with the :option:`--format=` option: @@ -86,7 +86,7 @@ Find [``-f``] .. option:: -f <file...> -The files are scanned, parsed and the names of design units are displayed. Design units marked with two stars are candidate to be at the apex of a design hierarchy. +The files are scanned, parsed and the names of design units are displayed. Design units marked with two stars are candidates to be at the apex of a design hierarchy. .. index:: cmd file chop @@ -95,9 +95,9 @@ Chop [``--chop``] .. option:: --chop <files...> -The provided files are read, and a file is written in the current directory for every design unit. Each filename is build according to the type: +The provided files are read, and a file is written in the current directory for every design unit. Each filename is built according to the type: -* For an entity declaration, a package declaration or a configuration the file name is :file:`NAME.vhdl`, where `NAME` is the name of the design unit. +* For an entity declaration, a package declaration, or a configuration the file name is :file:`NAME.vhdl`, where `NAME` is the name of the design unit. * For a package body, the filename is :file:`NAME-body.vhdl`. * Finally, for an architecture `ARCH` of an entity `ENTITY`, the filename is :file:`ENTITY-ARCH.vhdl`. @@ -105,7 +105,7 @@ Since the input files are parsed, this command aborts in case of syntax error. T Comments between design units are stored into the most adequate files. -This command may be useful to split big files, if your computer has not enough memory to compile such files. The size of the executable is reduced too. +This command may be useful to split big files, if your computer doesn't have enough memory to compile such files. The size of the executable is reduced too. .. index:: cmd file lines @@ -126,7 +126,7 @@ Bind [``--bind``] .. option:: --bind <[options] primary_unit [secondary_unit]> -Performs only the first stage of the elaboration command; the list of objects files is created but the executable is not built. This command should be used only when the main entry point is not GHDL. +Performs only the first stage of the elaboration command; the list of object files is created but the executable is not built. This command should be used only when the main entry point is not GHDL. .. index:: cmd GCC/LLVM linking @@ -151,29 +151,29 @@ Options .. option:: --mb-comments, -C -Allow multi-bytes chars in a comment +Allow multi-bytes chars in a comment. .. option:: --syn-binding -Use synthesizer rules for component binding. During elaboration, if a component is not bound to an entity using VHDL LRM rules, try to find in any known library an entity whose name is the same as the component name. +Use synthesizer rules for component binding. During elaboration, if a component is not bound to an entity using VHDL LRM rules, try to find in any known library an entity whose name is the same as the component name. -This rule is known as synthesizer rule. +This rule is known as the synthesizer rule. -There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known library. A known library is a library which has been named in your design. +There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known libraries. A known library is a library which has been named in your design. This option is only useful during elaboration. .. option:: --GHDL1<=COMMAND> -Use ``COMMAND`` as the command name for the compiler. If ``COMMAND`` is not a path, then it is searched in the path. +Use ``COMMAND`` as the command name for the compiler. If ``COMMAND`` is not a path, then it is searched in the path. .. option:: --AS<=COMMAND> -Use ``COMMAND`` as the command name for the assembler. If ``COMMAND`` is not a path, then it is searched in the path. The default is ``as``. +Use ``COMMAND`` as the command name for the assembler. If ``COMMAND`` is not a path, then it is searched in the path. The default is ``as``. .. option:: --LINK<=COMMAND> -Use ``COMMAND`` as the linker driver. If ``COMMAND`` is not a path, then it is searched in the path. The default is ``gcc``. +Use ``COMMAND`` as the linker driver. If ``COMMAND`` is not a path, then it is searched in the path. The default is ``gcc``. Passing options to other programs ================================= diff --git a/doc/references/ImplementationOfVHDL.rst b/doc/references/ImplementationOfVHDL.rst index 66246608d..90cedc825 100644 --- a/doc/references/ImplementationOfVHDL.rst +++ b/doc/references/ImplementationOfVHDL.rst @@ -4,7 +4,7 @@ Implementation of VHDL *************************** -This chapter describes several implementation defined aspect of VHDL in GHDL. +This chapter describes several implementation defined aspects of VHDL in GHDL. .. _VHDL_standards: @@ -33,7 +33,7 @@ VHDL standards .. index:: v08 -This is very unfortunate, but there are many versions of the VHDL +Unfortunately, there are many versions of the VHDL language, and they aren't backward compatible. The VHDL language was first standardized in 1987 by IEEE as IEEE 1076-1987, and @@ -43,11 +43,11 @@ since most of the VHDL tools are still based on this standard. Various problems of this first standard have been analyzed by experts groups to give reasonable ways of interpreting the unclear portions of the standard. -VHDL was revised in 1993 by IEEE as IEEE 1076-1993. This revision is still +VHDL was revised in 1993 by IEEE as IEEE 1076-1993. This revision is still well-known. Unfortunately, VHDL-93 is not fully compatible with VHDL-87, i.e. some perfectly -valid VHDL-87 programs are invalid VHDL-93 programs. Here are some of the +valid VHDL-87 programs are invalid VHDL-93 programs. Here are some of the reasons: * the syntax of file declaration has changed (this is the most visible source @@ -59,16 +59,16 @@ reasons: * rules have been added. Shared variables were replaced by protected types in the 2000 revision of -the VHDL standard. This modification is also known as 1076a. Note that this +the VHDL standard. This modification is also known as 1076a. Note that this standard is not fully backward compatible with VHDL-93, since the type of a shared variable must now be a protected type (there was no such restriction before). -Minors corrections were added by the 2002 revision of the VHDL standard. This +Minor corrections were added by the 2002 revision of the VHDL standard. This revision is not fully backward compatible with VHDL-00 since, for example, the value of the `'instance_name` attribute has slightly changed. -The latest version is 2008. Many features have been added, and GHDL +The latest version is 2008. Many features have been added, and GHDL doesn't implement all of them. You can select the VHDL standard expected by GHDL with the @@ -77,7 +77,7 @@ table below: 87 - Select VHDL-87 standard as defined by IEEE 1076-1987. LRM bugs corrected by + Select VHDL-87 standard as defined by IEEE 1076-1987. LRM bugs corrected by later revisions are taken into account. 93 @@ -89,20 +89,20 @@ table below: * VHDL-87 file declarations are accepted; - * default binding indication rules of VHDL-02 are used. Default binding rules + * default binding indication rules of VHDL-02 are used. Default binding rules are often used, but they are particularly obscure before VHDL-02. 00 Select VHDL-2000 standard, which adds protected types. 02 - Select VHDL-2002 standard + Select VHDL-2002 standard. 08 Select VHDL-2008 standard (partially implemented). -The 93, 93c, 00 and 02 standards are considered as compatible: you can -elaborate a design mixing these standards. However, 87, 93 and 08 are +The 93, 93c, 00 and 02 standards are considered compatible: you can +elaborate a design mixing these standards. However, 87, 93 and 08 are not compatible. .. _psl_implementation: @@ -117,11 +117,11 @@ As PSL annotations are embedded within comments, you must analyze and elaborate your design with option *-fpsl* to enable PSL annotations. A PSL assertion statement must appear within a comment that starts -with the `psl` keyword. The keyword must be followed (on the +with the `psl` keyword. The keyword must be followed (on the same line) by a PSL keyword such as `assert` or `default`. To continue a PSL statement on the next line, just start a new comment. -A PSL statement is considered as a process. So it is not allowed within +A PSL statement is considered a process, so it's not allowed within a process. All PSL assertions must be clocked (GHDL doesn't support unclocked assertion). @@ -135,7 +135,7 @@ You can either use a default clock like this: -- psl assert always -- a -> eventually! b; -or use a clocked expression (note the use of parenthesis): +or use a clocked expression (note the use of parentheses): .. code-block:: VHDL @@ -150,12 +150,12 @@ Source representation ===================== According to the VHDL standard, design units (i.e. entities, -architectures, packages, package bodies and configurations) may be +architectures, packages, package bodies, and configurations) may be independently analyzed. Several design units may be grouped into a design file. -In GHDL, a system file represents a design file. That is, a file compiled by +In GHDL, a system file represents a design file. That is, a file compiled by GHDL may contain one or more design units. It is common to have several design units in a design file. @@ -164,10 +164,10 @@ GHDL does not impose any restriction on the name of a design file (except that the filename may not contain any control character or spaces). -GHDL do not keep a binary representation of the design units analyzed like -other VHDL analyzers. The sources of the design units are re-read when -needed (for example, an entity is re-read when one of its architecture is -analyzed). Therefore, if you delete or modify a source file of a unit +GHDL does not keep a binary representation of the design units analyzed like +other VHDL analyzers. The sources of the design units are re-read when +needed (for example, an entity is re-read when one of its architectures is +analyzed). Therefore, if you delete or modify a source file of a unit analyzed, GHDL will refuse to use it. .. _Library_database: @@ -175,17 +175,17 @@ analyzed, GHDL will refuse to use it. Library database ================ -Each design unit analyzed is placed into a design library. By default, +Each design unit analyzed is placed into a design library. By default, the name of this design library is ``work``; however, this can be changed with the :option:`--work=NAME` option of GHDL. To keep the list of design units in a design library, GHDL creates -library files. The name of these files is :file:`NAME-objVER.cf`, where +library files. The name of these files is :file:`NAME-objVER.cf`, where `NAME` is the name of the library, and `VER` the VHDL version (87, 93 or 08) used to analyze the design units. -You don't have to know how to read a library file. You can display it -using the *-d* of `ghdl`. The file contains the name of the +You don't have to know how to read a library file. You can display it +using the *-d* of `ghdl`. The file contains the name of the design units, as well as the location and the dependencies. The format may change with the next version of GHDL. @@ -199,18 +199,18 @@ There are some restrictions on the entity being at the apex of a design hierarchy: * The generic must have a default value, and the value of a generic is its - default value; + default value. * The ports type must be constrained. Using vendor libraries ====================== -Many vendors libraries have been analyzed with GHDL. There are -usually no problems. Be sure to use the :option:`--work=` option. +Many vendors libraries have been analyzed with GHDL. There are +usually no problems. Be sure to use the :option:`--work=` option. However, some problems have been encountered. GHDL follows the VHDL LRM (the manual which defines VHDL) more -strictly than other VHDL tools. You could try to relax the +strictly than other VHDL tools. You could try to relax the restrictions by using the :option:`--std=93c`, :option:`-fexplicit`, :option:`-frelaxed-rules` and :option:`--warn-no-vital-generic`. @@ -230,13 +230,13 @@ Interfacing to other languages Interfacing with foreign languages is possible only on GNU/Linux systems. You can define a subprogram in a foreign language (such as `C` or -`Ada`) and import it in a VHDL design. +`Ada`) and import it into a VHDL design. Foreign declarations -------------------- Only subprograms (functions or procedures) can be imported, using the foreign -attribute. In this example, the `sin` function is imported: +attribute. In this example, the `sin` function is imported: .. code-block:: VHDL @@ -254,20 +254,20 @@ attribute. In this example, the `sin` function is imported: A subprogram is made foreign if the `foreign` attribute decorates -it. This attribute is declared in the 1993 revision of the -``std.standard`` package. Therefore, you cannot use this feature in +it. This attribute is declared in the 1993 revision of the +``std.standard`` package. Therefore, you cannot use this feature in VHDL 1987. -The decoration is achieved through an attribute specification. The +The decoration is achieved through an attribute specification. The attribute specification must be in the same declarative part as the -subprogram and must be after it. This is a general rule for specifications. +subprogram and must be after it. This is a general rule for specifications. The value of the specification must be a locally static string. -Even when a subprogram is foreign, its body must be present. However, since -it won't be called, you can made it empty or simply but an assertion. +Even when a subprogram is foreign, its body must be present. However, since +it won't be called, you can make it empty or simply put an assertion. The value of the attribute must start with ``VHPIDIRECT`` (an -upper-case keyword followed by one or more blanks). The linkage name of the +upper-case keyword followed by one or more blanks). The linkage name of the subprogram follows. .. _Restrictions_on_foreign_declarations: @@ -275,33 +275,33 @@ subprogram follows. Restrictions on foreign declarations ------------------------------------ -Any subprogram can be imported. GHDL puts no restrictions on foreign -subprograms. However, the representation of a type or of an interface in a -foreign language may be obscure. Most of non-composite types are easily imported: +Any subprogram can be imported. GHDL puts no restrictions on foreign +subprograms. However, the representation of a type or of an interface in a +foreign language may be obscure. Most non-composite types are easily imported: *integer types* - They are represented on a 32 bits word. This generally corresponds to + They are represented by a 32 bit word. This generally corresponds to `int` for `C` or `Integer` for `Ada`. *physical types* - They are represented on a 64 bits word. This generally corresponds to the + They are represented by a 64 bit word. This generally corresponds to the `long long` for `C` or `Long_Long_Integer` for `Ada`. *floating point types* - They are represented on a 64 bits floating point word. This generally + They are represented by a 64 bit floating point word. This generally corresponds to `double` for `C` or `Long_Float` for `Ada`. *enumeration types* - They are represented on 8 bits or 32 bits word, if the number of literals is - greater than 256. There is no corresponding C types, since arguments are + They are represented by an 8 bit word, or, if the number of literals is + greater than 256, by a 32 bit word. There is no corresponding C type, since arguments are not promoted. -Non-composite types are passed by value. For the `in` mode, this -corresponds to the `C` or `Ada` mechanism. The `out` and +Non-composite types are passed by value. For the `in` mode, this +corresponds to the `C` or `Ada` mechanism. The `out` and `inout` interfaces of non-composite types are gathered in a record and this record is passed by reference as the first argument to the -subprogram. As a consequence, you shouldn't use `in` and +subprogram. As a consequence, you shouldn't use `in` and `inout` modes in foreign subprograms, since they are not portable. Records are represented like a `C` structure and are passed by reference @@ -310,12 +310,12 @@ to subprograms. Arrays with static bounds are represented like a `C` array, whose length is the number of elements, and are passed by reference to subprograms. -Unconstrained array are represented by a fat pointer. Do not use unconstrained +Unconstrained arrays are represented by a fat pointer. Do not use unconstrained arrays in foreign subprograms. -Accesses to an unconstrained array is a fat pointer. Other accesses correspond to an address and are passed to a subprogram like other non-composite types. +Accesses to an unconstrained array are fat pointers. Other accesses correspond to an address and are passed to a subprogram like other non-composite types. -Files are represented by a 32 bits word, which corresponds to an index +Files are represented by a 32 bit word, which corresponds to an index in a table. .. _Linking_with_foreign_object_files: @@ -324,7 +324,7 @@ Linking with foreign object files --------------------------------- You may add additional files or options during the link using the -*-Wl,* of `GHDL`, as described in :ref:`Elaboration_command`. +*-Wl,* of `GHDL`, as described in :ref:`Elaboration:command`. For example:: ghdl -e -Wl,-lm math_tb @@ -339,7 +339,7 @@ Note the :file:`c` library is always linked with an executable. Starting a simulation from a foreign program -------------------------------------------- -You may run your design from an external program. You just have to call +You may run your design from an external program. You just have to call the ``ghdl_main`` function which can be defined: in C: @@ -355,12 +355,12 @@ in Ada: with System; ... function Ghdl_Main (Argc : Integer; Argv : System.Address) - return Integer; + return Integer; pragma import (C, Ghdl_Main, "ghdl_main"); This function must be called once, and returns 0 at the end of the simulation. -In case of failure, this function does not return. This has to be fixed. +In case of failure, this function does not return. This has to be fixed. .. _Linking_with_Ada: @@ -368,25 +368,25 @@ Linking with Ada ---------------- As explained previously in :ref:`Starting_a_simulation_from_a_foreign_program`, -you can start a simulation from an `Ada` program. However the build +you can start a simulation from an `Ada` program. However the build process is not trivial: you have to elaborate your `Ada` program and your `VHDL` design. -First, you have to analyze all your design files. In this example, we +First, you have to analyze all your design files. In this example, we suppose there is only one design file, :file:`design.vhdl`. :: $ ghdl -a design.vhdl -Then, bind your design. In this example, we suppose the entity at the +Then, bind your design. In this example, we suppose the entity at the design apex is ``design``. :: $ ghdl --bind design -Finally, compile, bind your `Ada` program at link it with your `VHDL` +Finally, compile, bind your `Ada` program and link it with your `VHDL` design:: $ gnatmake my_prog -largs `ghdl --list-link design` @@ -396,21 +396,21 @@ Using GRT from Ada ------------------ .. warning:: - This topic is only for advanced users knowing how to use `Ada` - and `GNAT`. This is provided only for reference, I have tested - this once before releasing `GHDL` 0.19 but this is not checked at + This topic is only for advanced users who know how to use `Ada` + and `GNAT`. This is provided only for reference; we have tested + this once before releasing `GHDL` 0.19, but this is not checked at each release. The simulator kernel of `GHDL` named :dfn:`GRT` is written in `Ada95` and contains a very light and slightly adapted version -of `VHPI`. Since it is an `Ada` implementation it is +of `VHPI`. Since it is an `Ada` implementation it is called :dfn:`AVHPI`. Although being tough, you may interface to `AVHPI`. For using `AVHPI`, you need the sources of `GHDL` and to recompile -them (at least the `GRT` library). This library is usually compiled with +them (at least the `GRT` library). This library is usually compiled with a `No_Run_Time` pragma, so that the user does not need to install the -`GNAT` runtime library. However, you certainly want to use the usual -runtime library and want to avoid this pragma. For this, reset the +`GNAT` runtime library. However, you certainly want to use the usual +runtime library and want to avoid this pragma. For this, reset the `GRT_PRAGMA_FLAG` variable. :: @@ -420,7 +420,7 @@ runtime library and want to avoid this pragma. For this, reset the Since `GRT` is a self-contained library, you don't want `gnatlink` to fetch individual object files (furthermore this -doesn't always work due to tricks used in `GRT`). For this, +doesn't always work due to tricks used in `GRT`). For this, remove all the object files and make the :file:`.ali` files read-only. :: @@ -429,12 +429,12 @@ remove all the object files and make the :file:`.ali` files read-only. $ chmod -w *.ali -You may then install the sources files and the :file:`.ali` files. I have never +You may then install the sources files and the :file:`.ali` files. I have never tested this step. You are now ready to use it. -For example, here is an example, :file:`test_grt.adb` which displays the top +Here is an example, :file:`test_grt.adb` which displays the top level design name. .. code-block:: Ada @@ -445,26 +445,26 @@ level design name. with Ghdl_Main; procedure Test_Grt is - -- VHPI handle. - H : VhpiHandleT; - Status : Integer; + -- VHPI handle. + H : VhpiHandleT; + Status : Integer; - -- Name. - Name : String (1 .. 64); - Name_Len : Integer; + -- Name. + Name : String (1 .. 64); + Name_Len : Integer; begin - -- Elaborate and run the design. - Status := Ghdl_Main (0, Null_Address); + -- Elaborate and run the design. + Status := Ghdl_Main (0, Null_Address); - -- Display the status of the simulation. - Put_Line ("Status is " & Integer'Image (Status)); + -- Display the status of the simulation. + Put_Line ("Status is " & Integer'Image (Status)); - -- Get the root instance. - Get_Root_Inst(H); + -- Get the root instance. + Get_Root_Inst(H); - -- Disp its name using vhpi API. - Vhpi_Get_Str (VhpiNameP, H, Name, Name_Len); - Put_Line ("Root instance name: " & Name (1 .. Name_Len)); + -- Disp its name using vhpi API. + Vhpi_Get_Str (VhpiNameP, H, Name, Name_Len); + Put_Line ("Root instance name: " & Name (1 .. Name_Len)); end Test_Grt; diff --git a/doc/references/ImplementationOfVITAL.rst b/doc/references/ImplementationOfVITAL.rst index 3cf99663c..77e7096c0 100644 --- a/doc/references/ImplementationOfVITAL.rst +++ b/doc/references/ImplementationOfVITAL.rst @@ -10,8 +10,8 @@ Implementation of VITAL .. index:: 1076.4 -This chapter describes how VITAL is implemented in GHDL. Support of VITAL is -really in a preliminary stage. Do not expect too much of it as now. +This chapter describes how VITAL is implemented in GHDL. Support of VITAL is +really in a preliminary stage. Do not expect too much of it as of right now. .. _vital_packages: @@ -21,14 +21,14 @@ VITAL packages The VITAL standard or IEEE 1076.4 was first published in 1995, and revised in 2000. -The version of the VITAL packages depends on the VHDL standard. VITAL +The version of the VITAL packages depends on the VHDL standard. VITAL 1995 packages are used with the VHDL 1987 standard, while VITAL 2000 -packages are used with other standards. This choice is based on the +packages are used with other standards. This choice is based on the requirements of VITAL: VITAL 1995 requires the models follow the VHDL 1987 standard, while VITAL 2000 requires the models follow VHDL 1993. The VITAL 2000 packages were slightly modified so that they conform to -the VHDL 1993 standard (a few functions are made pure and a few one +the VHDL 1993 standard (a few functions are made pure and a few impure). .. _vhdl_restrictions_for_vital: @@ -40,18 +40,18 @@ The VITAL standard (partially) implemented is the IEEE 1076.4 standard published in 1995. This standard defines restriction of the VHDL language usage on VITAL -model. A :dfn:`VITAL model` is a design unit (entity or architecture) +model. A :dfn:`VITAL model` is a design unit (entity or architecture) decorated by the `VITAL_Level0` or `VITAL_Level1` attribute. These attributes are defined in the `ieee.VITAL_Timing` package. -Currently, only VITAL level 0 checks are implemented. VITAL level 1 models +Currently, only VITAL level 0 checks are implemented. VITAL level 1 models can be analyzed, but GHDL doesn't check they comply with the VITAL standard. Moreover, GHDL doesn't check (yet) that timing generics are not read inside a VITAL level 0 model prior the VITAL annotation. -The analysis of a non-conformant VITAL model fails. You can disable the -checks of VITAL restrictions with the *--no-vital-checks*. Even when +The analysis of a non-conformant VITAL model fails. You can disable the +checks of VITAL restrictions with the *--no-vital-checks*. Even when restrictions are not checked, SDF annotation can be performed. .. _backannotation: @@ -64,31 +64,31 @@ Backannotation :dfn:`Backannotation` is the process of setting VITAL generics with timing information provided by an external files. -The external files must be SDF (Standard Delay Format) files. GHDL -supports a tiny subset of SDF version 2.1, other version number can be -used, provided no features added by the next version are used. +The external files must be SDF (Standard Delay Format) files. GHDL +supports a tiny subset of SDF version 2.1. Other version numbers can be +used, provided no features added by later versions are used. Hierarchical instance names are not supported. However you can use a list of -instances. If there is no instance, the top entity will be annotated and -the celltype must be the name of the top entity. If there is at least one +instances. If there is no instance, the top entity will be annotated and +the celltype must be the name of the top entity. If there is at least one instance, the last instance name must be a component instantiation label, and the celltype must be the name of the component declaration instantiated. -Instances being annotated are not required to be VITAL compliant. However +Instances being annotated are not required to be VITAL compliant. However generics being annotated must follow rules of VITAL (e.g., type must be a suitable vital delay type). Currently, only timing constraints applying on a timing generic of type -`VitalDelayType01` has been implemented. This SDF annotator is -just a proof of concept. Features will be added with the following GHDL +`VitalDelayType01` has been implemented. This SDF annotator is +just a proof of concept. Features will be added with the following GHDL release. Negative constraint calculation =============================== -Negative constraint delay adjustment are necessary to handle negative -constraint such as a negative setup time. This step is defined in the VITAL +Negative constraint delay adjustments are necessary to handle negative +constraints such as a negative setup time. This step is defined in the VITAL standard and should occur after backannotation. -GHDL does not do negative constraint calculation. It fails to handle models -with negative constraint. I hope to be able to add this phase soon. +GHDL does not do negative constraint calculation. It fails to handle models +with negative constraint. I hope to be able to add this phase soon. diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst index dd50a5874..e64c695c6 100644 --- a/doc/using/InvokingGHDL.rst +++ b/doc/using/InvokingGHDL.rst @@ -13,10 +13,10 @@ The form of the :program:`ghdl` command is ``ghdl command [options...]``. There If the number of options is large and the command line length is beyond the system limit, you can use a response file. An argument that starts with a ``@`` is considered as a response file; it is replaced by arguments read from the file (separated by blanks and end of line). .. HINT:: - Only the most common commands and options are shown here. For most advanced and experimental features see section :ref:`REF:Command`. + Only the most common commands and options are shown here. For the most advanced and experimental features see section :ref:`REF:Command`. .. WARNING:: - During analysis and elaboration GHDL may read the ``std`` and ``ieee`` files. The location of these files is based on the prefix, which is (in priority order): + During analysis and elaboration GHDL may read the ``std`` and ``ieee`` files. The location of these files is based on the prefix, which is (in order of priority): * the :option:`--PREFIX` command line option * the :envvar:`GHDL_PREFIX` environment variable @@ -27,7 +27,7 @@ The form of the :program:`ghdl` command is ``ghdl command [options...]``. There Design building commands ======================== -The mostly used commands of GHDL are those to analyze and elaborate a design. +The most commonly used commands of GHDL are those to analyze and elaborate a design. .. index:: cmd analysis @@ -39,17 +39,19 @@ Analysis [``-a``] Analyzes/compiles one or more files, and creates an object file for each source file. Any argument starting with a dash is an option, the others are filenames. No options are allowed after a filename argument. GHDL analyzes each filename in the given order, and stops the analysis in case of error (remaining files are not analyzed). -See :ref:`GHDL_options`, for details on the GHDL options. For example, to produce debugging information such as line numbers, use: ``ghdl -a -g my_design.vhdl``. +See :ref:`GHDL:options`, for details on the GHDL options. For example, to produce debugging information such as line numbers, use: ``ghdl -a -g my_design.vhdl``. .. index:: cmd elaboration +.. _Elaboration:command: + Elaboration [``-e``] ------------------------ .. option:: -e <[options...] primary_unit [secondary_unit]> -Re-analyzes all the configurations, entities, architectures and package declarations, and creates the default configurations and the default binding indications according to the LRM rules. It also generates the list of objects files required for the executable. Then, it links all these files with the runtime library. The actual elaboration is performed at runtime. +Re-analyzes all the configurations, entities, architectures and package declarations, and creates the default configurations and the default binding indications according to the LRM rules. It also generates the list of object files required for the executable. Then, it links all these files with the runtime library. The actual elaboration is performed at runtime. * The elaboration command, :option:`-e`, must be followed by a name of either: @@ -57,11 +59,11 @@ Re-analyzes all the configurations, entities, architectures and package declarat * an entity unit * an entity unit followed by a name of an architecture unit -Name of the units must be a simple name, without any dot. You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in :ref:`GHDL_options`. See section ':ref:`Top_entity`', for the restrictions on the root design of a hierarchy. +Name of the units must be a simple name, without any dot. You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in :ref:`GHDL:options`. See section :ref:`Top_entity`, for the restrictions on the root design of a hierarchy. -* If the GCC/LLVM backend was enabled during the compilation of GHDL, the elaboration command creates an executable containing the code of the VHDL sources, the elaboration code and simulation code to execute a design hierarchy. The executable is created in the current directory and the the filename is the name of the primary unit, or for the later case, the concatenation of the name of the primary unit, a dash, and the name of the secondary unit (or architecture). Option :option:`-o` followed by a filename can override the default executable filename. +* If the GCC/LLVM backend was enabled during the compilation of GHDL, the elaboration command creates an executable containing the code of the VHDL sources, the elaboration code and simulation code to execute a design hierarchy. The executable is created in the current directory and the the filename is the name of the primary unit, or for the latter case, the concatenation of the name of the primary unit, a dash, and the name of the secondary unit (or architecture). Option :option:`-o` followed by a filename can override the default executable filename. -* If mcode is used, this command elaborates the design but does not generate anything. Since the run command also elaborates the design, this con be skipped. +* If mcode is used, this command elaborates the design but does not generate anything. Since the run command also elaborates the design, this can be skipped. .. index:: cmd run @@ -82,7 +84,7 @@ This command exists for three reasons: * It is coherent with the :option:`-a` and :option:`-e` commands. * It works with mcode implementation, where the executable code is generated in memory. -See section ':ref:`USING:Simulation`', for details on options. +See section :ref:`USING:Simulation`, for details on options. .. index:: cmd elaborate and run @@ -124,10 +126,10 @@ The advantages over the traditional approach (analyze and then elaborate) are: * The compilation cycle is achieved in one command. * Since the files are only parsed once, the compilation cycle may be faster. * You don't need to know an analysis order. -* This command produces smaller executable, since unused units and subprograms do not generate code. +* This command produces a smaller executable, since unused units and subprograms do not generate code. .. HINT:: - However, you should know that currently most of the time is spent in code generation and the analyze and elaborate command generate code for all units needed, even units of ``std`` and ``ieee`` libraries. Therefore, according to the design, the time for this command may be higher than the time for the analyze command followed by the elaborate command. + However, you should know that most of the time is spent in code generation and the analyze and elaborate command generates code for all units needed, even units of ``std`` and ``ieee`` libraries. Therefore, according to the design, the time for this command may be higher than the time for the analyze command followed by the elaborate command. .. WARNING:: This command is still under development. In case of problems, you should go back to the traditional way. @@ -136,7 +138,7 @@ The advantages over the traditional approach (analyze and then elaborate) are: Design rebuilding commands ========================== -Analyzing and elaborating a design consisting in several files can be tricky, due to dependencies. GHDL has a few commands to rebuild a design. +Analyzing and elaborating a design consisting of several files can be tricky, due to dependencies. GHDL has a few commands to rebuild a design. .. index:: cmd importing files @@ -146,7 +148,7 @@ Import [``-i``] .. option:: -i <[options] file...> -All the files specified in the command line are scanned, parsed and added in the libraries but as not yet analyzed. No object files are created. It's purpose is to localize design units in the design files. The make command will then be able to recursively build a hierarchy from an entity name or a configuration name. +All the files specified in the command line are scanned, parsed and added into the libraries but as not yet analyzed. No object files are created. Its purpose is to localize design units in the design files. The make command will then be able to recursively build a hierarchy from an entity name or a configuration name. .. HINT:: @@ -163,14 +165,14 @@ Make [``-m``] .. option:: -m <[options] primary [secondary]> -Analyze automatically outdated files and elaborate a design. The primary unit denoted by the ``primary`` argument must already be known by the system, either because you have already analyzed it (even if you have modified it) or because you have imported it. A file may be outdated because it has been modified (e.g. you just have edited it), or because a design unit contained in the file depends on a unit which is outdated. This rule is of course recursive. +Analyze automatically outdated files and elaborate a design. The primary unit denoted by the ``primary`` argument must already be known by the system, either because you have already analyzed it (even if you have modified it) or because you have imported it. A file may be outdated because it has been modified (e.g. you have just edited it), or because a design unit contained in the file depends on a unit which is outdated. This rule is of course recursive. * With option :option:`--bind`, GHDL will stop before the final linking step. This is useful when the main entry point is not GHDL and you're linking GHDL object files into a foreign program. -* With option :option:`-f` (force), GHDL analyzes all the units of the work library needed to create the design hierarchy. Not outdated units are recompiled. This is useful if you want to compile a design hierarchy with new compilation flags (for example, to add the *-g* debugging option). +* With option :option:`-f` (force), GHDL analyzes all the units of the work library needed to create the design hierarchy. Outdated units are recompiled. This is useful if you want to compile a design hierarchy with new compilation flags (for example, to add the *-g* debugging option). The make command will only re-analyze design units in the work library. GHDL fails if it has to analyze an outdated unit from another library. -The purpose of this command is to be able to compile a design without prior knowledge of file order. In the VHDL model, some units must be analyzed before others (e.g. an entity before its architecture). It might be a nightmare to analyze a full design of several files, if you don't have the ordered list of file. This command computes an analysis order. +The purpose of this command is to be able to compile a design without prior knowledge of file order. In the VHDL model, some units must be analyzed before others (e.g. an entity before its architecture). It might be a nightmare to analyze a full design of several files if you don't have the ordered list of files. This command computes an analysis order. The make command fails when a unit was not previously parsed. For example, if you split a file containing several design units into several files, you must either import these new files or analyze them so that GHDL knows in which file these units are. @@ -200,6 +202,8 @@ Generate a Makefile containing only dependencies to build a design unit. This command works like the make and gen-makefile commands (see :option:`-m`), but instead of a full makefile only dependencies without rules are generated on the standard output. Theses rules can then be integrated in another Makefile. +.. _GHDL:options: + Options ======= @@ -208,27 +212,27 @@ Options .. index:: IEEE 1076.3 .. index:: 1076.3 -.. HINT:: Besides the options described below, `GHDL` passes any debugging options (those that begin with :option:`-g`) and optimizations options (those that begin with :option:`-O` or :option:`-f`) to `GCC`. Refer to the `GCC` manual for details. +.. HINT:: Besides the options described below, `GHDL` passes any debugging options (those that begin with :option:`-g`) and optimizations options (those that begin with :option:`-O` or :option:`-f`) to `GCC`. Refer to the `GCC` manual for details. .. index:: WORK library .. option:: --work<=NAME> - Specify the name of the ``WORK`` library. Analyzed units are always placed in the library logically named ``WORK``. With this option, you can set its name. By default, the name is ``work``. + Specify the name of the ``WORK`` library. Analyzed units are always placed in the library logically named ``WORK``. With this option, you can set its name. By default, the name is ``work``. - `GHDL` checks whether ``WORK`` is a valid identifier. Although being more or less supported, the ``WORK`` identifier should not be an extended identifier, since the filesystem may prevent it from correctly working (due to case sensitivity or forbidden characters in filenames). + `GHDL` checks whether ``WORK`` is a valid identifier. Although being more or less supported, the ``WORK`` identifier should not be an extended identifier, since the filesystem may prevent it from working correctly (due to case sensitivity or forbidden characters in filenames). - `VHDL` rules forbid you to add units to the ``std`` library. Furthermore, you should not put units in the ``ieee`` library. + `VHDL` rules forbid you from adding units to the ``std`` library. Furthermore, you should not put units in the ``ieee`` library. .. option:: --workdir<=DIR> - Specify the directory where the ``WORK`` library is located. When this option is not present, the ``WORK`` library is in the current directory. The object files created by the compiler are always placed in the same directory as the ``WORK`` library. + Specify the directory where the ``WORK`` library is located. When this option is not present, the ``WORK`` library is in the current directory. The object files created by the compiler are always placed in the same directory as the ``WORK`` library. Use option :option:`-P` to specify where libraries other than ``WORK`` are placed. .. option:: --std<=STD> - Specify the standard to use. By default, the standard is ``93c``, which means VHDL-93 accepting VHDL-87 syntax. For details on ``STD`` values see section ':ref:`VHDL_standards`'. + Specify the standard to use. By default, the standard is ``93c``, which means VHDL-93 accepting VHDL-87 syntax. For details on ``STD`` values see section :ref:`VHDL_standards`. .. option:: --ieee<=VER> @@ -239,18 +243,18 @@ Options Select the ``IEEE`` library to use. ``VER`` must be one of: none - Do not supply an `IEEE` library. Any library clause with the ``IEEE`` - identifier will fail, unless you have created by your own a library with + Do not supply an `IEEE` library. Any library clause with the ``IEEE`` + identifier will fail, unless you have created your own library with the `IEEE` name. standard Supply an `IEEE` library containing only packages defined by - ``ieee`` standards. Currently, there are the multivalue logic system - packages ``std_logic_1164`` defined by IEEE 1164, the synthesis - packages , ``numeric_bit`` and ``numeric_std`` defined by IEEE + ``ieee`` standards. Currently, there are the multivalue logic system + package ``std_logic_1164`` defined by IEEE 1164, the synthesis + packages ``numeric_bit`` and ``numeric_std`` defined by IEEE 1076.3, and the ``vital`` packages ``vital_timing`` and - ``vital_primitives``, defined by IEEE 1076.4. The version of these - packages is defined by the VHDL standard used. See section ':ref:`VITAL_packages`', + ``vital_primitives``, defined by IEEE 1076.4. The version of these + packages is defined by the VHDL standard used. See section :ref:`VITAL_packages`, for more details. synopsys @@ -258,14 +262,14 @@ Options ``std_logic_arith``, ``std_logic_signed``, ``std_logic_unsigned``, ``std_logic_textio``. - These packages were created by some companies, and are popular. However + These packages were created by some companies, and are popular. However they are not standard packages, and have been placed in the `IEEE` library without the permission from the ``ieee``. mentor Supply the standard packages and the following additional package: - ``std_logic_arith``. The package is a slight variation of a definitely - not standard but widely mis-used package. + ``std_logic_arith``. This package is a slight variation of a definitely + not standard but widely misused package. To avoid errors, you must use the same `IEEE` library for all units of your design, and during elaboration. @@ -273,7 +277,7 @@ Options .. option:: -P<DIRECTORY> Add `DIRECTORY` to the end of the list of directories to be searched for - library files. A library is searched in `DIRECTORY` and also in + library files. A library is searched in `DIRECTORY` and also in `DIRECTORY/LIB/vVV` (where `LIB` is the name of the library and `VV` the vhdl standard). @@ -285,34 +289,34 @@ Options When two operators are overloaded, give preference to the explicit declaration. This may be used to avoid the most common pitfall of the ``std_logic_arith`` - package. See section ':ref:`IEEE_library_pitfalls`', for an example. + package. See section :ref:`IEEE_library_pitfalls`, for an example. -.. WARNING:: This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule. When set, an operator can be silently overridden in another package. You'd better fix your design and use the ``numeric_std`` package. +.. WARNING:: This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule. When set, an operator can be silently overridden in another package. You'd do better to fix your design and use the ``numeric_std`` package. .. option:: -frelaxed-rules - Within an object declaration, allow to reference the name (which references the hidden declaration). This ignores the error in the following code: + Within an object declaration, allow references to the name (which references the hidden declaration). This ignores the error in the following code: .. code-block:: VHDL - package pkg1 is + package pkg1 is type state is (state1, state2, state3); - end pkg1; + end pkg1; - use work.pkg1.all; - package pkg2 is + use work.pkg1.all; + package pkg2 is constant state1 : state := state1; - end pkg2; + end pkg2; Some code (such as Xilinx packages) have such constructs, which are valid. - (The scope of the ``state1`` constant start at the `constant` word. Because the constant ``state1`` and the enumeration literal ``state1`` are homograph, the enumeration literal is hidden in the immediate scope of the constant). + (The scope of the ``state1`` constant starts at the `constant` keyword. Because the constant ``state1`` and the enumeration literal ``state1`` are homographs, the enumeration literal is hidden in the immediate scope of the constant). This option also relaxes the rules about pure functions. Violations result in warnings instead of errors. .. option:: -fpsl - Enable parsing of PSL assertions within comments. See section ':ref:`PSL_implementation`' for more details. + Enable parsing of PSL assertions within comments. See section :ref:`PSL_implementation` for more details. .. option:: --no-vital-checks .. option:: --vital-checks @@ -321,7 +325,7 @@ Options Checks are performed only when a design unit is decorated by a VITAL attribute. The VITAL attributes are ``VITAL_Level0`` and ``VITAL_Level1``, both declared in the ``ieee.VITAL_Timing`` package. - Currently, VITAL checks are only partially implemented. See section ':ref:`VHDL_restrictions_for_VITAL`' for more details. + Currently, VITAL checks are only partially implemented. See section :ref:`VHDL_restrictions_for_VITAL` for more details. .. option:: --PREFIX<=PATH> @@ -338,7 +342,7 @@ Warnings Some constructions are not erroneous but dubious. Warnings are diagnostic messages that report such constructions. Some warnings are reported only during analysis, others during elaboration. .. HINT:: - You could disable a warning by using the ``--warn-no-XXX`` or ``-Wno-XX`` instead of ``--warn-XXX`` or ``-WXXX``. + You could disable a warning by using the ``--warn-no-XXX`` or ``-Wno-XXX`` instead of ``--warn-XXX`` or ``-WXXX``. .. option:: --warn-reserved @@ -346,13 +350,13 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag .. option:: --warn-default-binding - During analyze, warns if a component instantiation has neither configuration specification nor default binding. This may be useful if you want to detect during analyze possibly unbound component if you don't use configuration. See section ':ref:`VHDL_standards`' for more details about default binding rules. + During analyze, warns if a component instantiation has neither configuration specification nor default binding. This may be useful if you want to detect during analyze possibly unbound components if you don't use configuration. See section :ref:`VHDL_standards` for more details about default binding rules. .. option:: --warn-binding - During elaboration, warns if a component instantiation is not bound (and not explicitly left unbound). Also warns if a port of an entity is not bound in a configuration specification or in a component configuration. This warning is enabled by default, since default binding rules are somewhat complex and an unbound component is most often unexpected. + During elaboration, warns if a component instantiation is not bound (and not explicitly left unbound). Also warns if a port of an entity is not bound in a configuration specification or in a component configuration. This warning is enabled by default, since default binding rules are somewhat complex and an unbound component is most often unexpected. - However, warnings are even emitted if a component instantiation is inside a generate statement. As a consequence, if you use the conditional generate statement to select a component according to the implementation, you will certainly get warnings. + However, warnings are still emitted if a component instantiation is inside a generate statement. As a consequence, if you use the conditional generate statement to select a component according to the implementation, you will certainly get warnings. .. option:: --warn-library @@ -360,18 +364,18 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag .. option:: --warn-vital-generic - Warns if a generic name of a vital entity is not a vital generic name. This + Warns if a generic name of a vital entity is not a vital generic name. This is set by default. .. option:: --warn-delayed-checks - Warns for checks that cannot be done during analysis time and are postponed to elaboration time. This is because not all procedure bodies are available during analysis (either because a package body has not yet been analysed or because `GHDL` doesn't read not required package bodies). + Warns for checks that cannot be done during analysis time and are postponed to elaboration time. This is because not all procedure bodies are available during analysis (either because a package body has not yet been analysed or because `GHDL` doesn't read not required package bodies). - These are checks for no wait statement in a procedure called in a sensitized process and checks for pure rules of a function. + These are checks for no wait statements in a procedure called in a sensitized process and checks for pure rules of a function. .. option:: --warn-body - Emit a warning if a package body which is not required is analyzed. If a package does not declare a subprogram or a deferred constant, the package does not require a body. + Emit a warning if a package body which is not required is analyzed. If a package does not declare a subprogram or a deferred constant, the package does not require a body. .. option:: --warn-specs @@ -391,7 +395,7 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag .. option:: --warn-parenthesis - Emit a warning in case of weird use of parenthesis + Emit a warning in case of weird use of parentheses. .. option:: --warn-runtime-error @@ -410,7 +414,7 @@ Diagnostics Control .. option:: -fdiagnostics-show-option .. option:: -fno-diagnostics-show-option - Control whether the warning option is displayed at the end of warning messages, so that user can easily know how to disable it. + Control whether the warning option is displayed at the end of warning messages, so that the user can easily know how to disable it. Library commands @@ -453,7 +457,7 @@ Remove [``--remove``] .. option:: --remove <[options]> -Do like the clean command but remove the library too. Note that after removing a design library, the files are not +Acts like the clean command but removes the library too. Note that after removing a design library, the files are not known anymore by GHDL. @@ -464,7 +468,7 @@ Copy [``--copy``] .. option:: --copy <--work=name [options]> -Make a local copy of an existing library. This is very useful if you want to add unit to the ``ieee`` library: +Make a local copy of an existing library. This is very useful if you want to add units to the ``ieee`` library: .. code-block:: shell @@ -475,7 +479,7 @@ Make a local copy of an existing library. This is very useful if you want to ad VPI build commands ================== -These commands simplify the compile and the link of a user vpi module. They are all wrapper: the arguments are in fact a whole command line that is executed with additional switches. Currently a unix-like compiler (like `cc`, `gcc` or `clang`) is expected: the additional switches use their syntax. The only option is `-v` which displays the +These commands simplify the compile and the link of a user vpi module. They are all wrappers: the arguments are in fact a whole command line that is executed with additional switches. Currently a unix-like compiler (like `cc`, `gcc` or `clang`) is expected: the additional switches use their syntax. The only option is `-v` which displays the command before its execution. @@ -486,7 +490,7 @@ compile [``--vpi-compile``] .. option:: --vpi-compile <command> -Add include path to the command and execute it:: +Add an include path to the command and execute it:: ghdl --vpi-compile command @@ -511,7 +515,7 @@ link [``--vpi-link``] .. option:: --vpi-link <command> -Add library path and name to the command and execute it:: +Add a library path and name to the command and execute it:: ghdl --vpi-link command @@ -572,7 +576,7 @@ Display the library directory added by the link flags. IEEE library pitfalls ===================== -When you use options :option:`--ieee=synopsys` or :option:`--ieee=mentor`, the ``ieee`` library contains non standard packages such as ``std_logic_arith``. These packages are not standard because there are not described by an IEEE standard, even if they have been put in the `IEEE` library. Furthermore, they are not really de-facto standard, because there are slight differences between the packages of Mentor and those of Synopsys. Furthermore, since they are not well-thought, their use has pitfalls. For example, this description has error during compilation: +When you use options :option:`--ieee=synopsys` or :option:`--ieee=mentor`, the ``ieee`` library contains non standard packages such as ``std_logic_arith``. These packages are not standard because there are not described by an IEEE standard, even if they have been put in the `IEEE` library. Furthermore, they are not really de-facto standard, because there are slight differences between the packages of Mentor and those of Synopsys. Furthermore, since they are not well thought out, their use has pitfalls. For example, this description has an error during compilation: .. code-block:: VHDL @@ -581,9 +585,9 @@ When you use options :option:`--ieee=synopsys` or :option:`--ieee=mentor`, the ` -- A counter from 0 to 10. entity counter is - port (val : out std_logic_vector (3 downto 0); - ck : std_logic; - rst : std_logic); + port (val : out std_logic_vector (3 downto 0); + ck : std_logic; + rst : std_logic); end counter; library ieee; @@ -591,27 +595,26 @@ When you use options :option:`--ieee=synopsys` or :option:`--ieee=mentor`, the ` architecture bad of counter is - signal v : std_logic_vector (3 downto 0); + signal v : std_logic_vector (3 downto 0); begin - process (ck, rst) - begin - if rst = '1' then + process (ck, rst) + begin + if rst = '1' then + v <= x"0"; + elsif rising_edge (ck) then + if v = "1010" then -- Error v <= x"0"; - elsif rising_edge (ck) then - if v = "1010" then -- Error - v <= x"0"; - else - v <= v + 1; - end if; - end if; - end process; - - val <= v; + else + v <= v + 1; + end if; + end if; + end process; + + val <= v; end bad; -When you analyze this design, GHDL does not accept it (too long lines -have been split for readability): +When you analyze this design, GHDL does not accept it (two long lines have been split for readability): .. code-block:: shell @@ -624,12 +627,12 @@ have been split for readability): [std_logic_vector, std_logic_vector return boolean] ../translate/ghdldrv/ghdl: compilation error -Indeed, the `"="` operator is defined in both packages, and both are visible at the place it is used. The first declaration is an implicit one, which occurs when the `std_logic_vector` type is declared and is an element to element comparison, the second one is an explicit declared function, with the semantic of an unsigned comparison. +Indeed, the `"="` operator is defined in both packages, and both are visible at the place it is used. The first declaration is an implicit one, which occurs when the `std_logic_vector` type is declared and is an element to element comparison. The second one is an explicit declared function, with the semantics of an unsigned comparison. -With some analyser, the explicit declaration has priority over the implicit declaration, and this design can be analyzed without error. However, this is not the rule given by the VHDL LRM, and since GHDL follows these rules, +With some analysers, the explicit declaration has priority over the implicit declaration, and this design can be analyzed without error. However, this is not the rule given by the VHDL LRM, and since GHDL follows these rules, it emits an error. -You can force GHDL to use this rule with the *-fexplicit* option (see :ref:`GHDL_options` for further details). However it is easy to fix this error, by using a selected name: +You can force GHDL to use this rule with the *-fexplicit* option (see :ref:`GHDL:options` for further details). However it is easy to fix this error, by using a selected name: .. code-block:: VHDL @@ -638,25 +641,25 @@ You can force GHDL to use this rule with the *-fexplicit* option (see :ref:`GHDL architecture fixed_bad of counter is - signal v : std_logic_vector (3 downto 0); + signal v : std_logic_vector (3 downto 0); begin - process (ck, rst) - begin - if rst = '1' then + process (ck, rst) + begin + if rst = '1' then + v <= x"0"; + elsif rising_edge (ck) then + if ieee.std_logic_unsigned."=" (v, "1010") then v <= x"0"; - elsif rising_edge (ck) then - if ieee.std_logic_unsigned."=" (v, "1010") then - v <= x"0"; - else - v <= v + 1; - end if; - end if; - end process; - - val <= v; + else + v <= v + 1; + end if; + end if; + end process; + + val <= v; end fixed_bad; -It is better to only use the standard packages defined by IEEE, which provides the same functionalities: +It is better to only use the standard packages defined by IEEE, which provide the same functionalities: .. code-block:: VHDL @@ -665,22 +668,22 @@ It is better to only use the standard packages defined by IEEE, which provides t architecture good of counter is - signal v : unsigned (3 downto 0); + signal v : unsigned (3 downto 0); begin - process (ck, rst) - begin - if rst = '1' then + process (ck, rst) + begin + if rst = '1' then + v <= x"0"; + elsif rising_edge (ck) then + if v = "1010" then v <= x"0"; - elsif rising_edge (ck) then - if v = "1010" then - v <= x"0"; - else - v <= v + 1; - end if; - end if; - end process; - - val <= std_logic_vector (v); + else + v <= v + 1; + end if; + end if; + end process; + + val <= std_logic_vector (v); end good; .. index:: Math_Real diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst index a1afa00b2..279969db1 100644 --- a/doc/using/QuickStartGuide.rst +++ b/doc/using/QuickStartGuide.rst @@ -9,27 +9,27 @@ In this chapter, you will learn how to use `GHDL` by working on a few examples. The `'Hello world'` program =========================== -To illustrate the large purpose of `VHDL`, here is a commented `'Hello world'` program which saved in a file named :file:`hello.vhdl`: +To illustrate the general purpose of `VHDL`, here is a commented `'Hello world'` program which is saved in a file named :file:`hello.vhdl`: .. code-block:: VHDL - -- Hello world program. - use std.textio.all; -- Imports the standard textio package. + -- Hello world program + use std.textio.all; -- Imports the standard textio package. - -- Defines a design entity, without any ports. - entity hello_world is - end hello_world; + -- Defines a design entity, without any ports. + entity hello_world is + end hello_world; - architecture behaviour of hello_world is - begin - process - variable l : line; - begin - write (l, String'("Hello world!")); - writeline (output, l); - wait; - end process; - end behaviour; + architecture behaviour of hello_world is + begin + process + variable l : line; + begin + write (l, String'("Hello world!")); + writeline (output, l); + wait; + end process; + end behaviour; .. TIP:: @@ -42,13 +42,13 @@ To illustrate the large purpose of `VHDL`, here is a commented `'Hello world'` p .. code-block:: shell - Hello world! + Hello world! .. HINT:: If a GCC/LLVM variant of `GHDL` is used: - * `Analysis` generates a file, :file:`hello.o`, which is the object file corresponding to your `VHDL` program. This is not created with mcode. - * The elaboration step is compulsory after the analysis and prior to launching the simulation; This wil generate an executable binary named :file:`hello_world`. + * `Analysis` generates a file, :file:`hello.o`, which is the object file corresponding to your `VHDL` program. This is not created with mcode. + * The elaboration step is mandatory after running the analysis and prior to launching the simulation. This will generate an executable binary named :file:`hello_world`. * As a result, :option:`-r` is just a passthrough to the binary generated in the `elaboration`. Therefore, the executable can be run directly, ``./hello_world``. See :option:`-r` for more informartion. .. HINT:: :option:`-e` can be bypassed with mcode, since :option:`-r` actually elaborates the design and saves it on memory before running the simulation. But you can still use it to check for some elaboration problems. @@ -77,86 +77,86 @@ The `heartbeat` program A full adder ============ -VHDL is generally used for hardware design. This example starts with a `full adder <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ described in a file named :file:`adder.vhdl`: +VHDL is generally used for hardware design. This example starts with a `full adder <https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder>`_ described in a file named :file:`adder.vhdl`: .. code-block:: VHDL - entity adder is - -- `i0`, `i1` and the carry-in `ci` are inputs of the adder. - -- `s` is the sum output, `co` is the carry-out. - port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); - end adder; + entity adder is + -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder. + -- `s` is the sum output, `co` is the carry-out. + port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); + end adder; - architecture rtl of adder is - begin - -- This full-adder architecture contains two concurrent assignment. - -- Compute the sum. - s <= i0 xor i1 xor ci; - -- Compute the carry. - co <= (i0 and i1) or (i0 and ci) or (i1 and ci); - end rtl; + architecture rtl of adder is + begin + -- This full-adder architecture contains two concurrent assignments. + -- Compute the sum. + s <= i0 xor i1 xor ci; + -- Compute the carry. + co <= (i0 and i1) or (i0 and ci) or (i1 and ci); + end rtl; -You can analyze this design file, ``ghdl -a adder.vhdl``, and try to execute the `adder` design. But this is useless, since nothing externally visible will happen. In order to check this full adder, a :dfn:`testbench` has to be run. This testbench is very simple, since the adder is also simple: it checks exhaustively all inputs. Note that only the behaviour is tested, timing constraints are not checked. A file named :file:`adder_tb.vhdl` contains the testbench for the adder: +You can analyze this design file, ``ghdl -a adder.vhdl``, and try to execute the `adder` design. But this is useless, since nothing externally visible will happen. In order to check this full adder, a :dfn:`testbench` has to be run. This testbench is very simple, since the adder is also simple: it checks exhaustively all inputs. Note that only the behaviour is tested, timing constraints are not checked. A file named :file:`adder_tb.vhdl` contains the testbench for the adder: .. code-block:: VHDL - -- A testbench has no ports. - entity adder_tb is - end adder_tb; - - architecture behav of adder_tb is - -- Declaration of the component that will be instantiated. - component adder - port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); - end component; - - -- Specifies which entity is bound with the component. - for adder_0: adder use entity work.adder; - signal i0, i1, ci, s, co : bit; - begin - -- Component instantiation. - adder_0: adder port map (i0 => i0, i1 => i1, ci => ci, - s => s, co => co); - - -- This process does the real job. - process - type pattern_type is record - -- The inputs of the adder. - i0, i1, ci : bit; - -- The expected outputs of the adder. - s, co : bit; - end record; - -- The patterns to apply. - type pattern_array is array (natural range <>) of pattern_type; - constant patterns : pattern_array := - (('0', '0', '0', '0', '0'), - ('0', '0', '1', '1', '0'), - ('0', '1', '0', '1', '0'), - ('0', '1', '1', '0', '1'), - ('1', '0', '0', '1', '0'), - ('1', '0', '1', '0', '1'), - ('1', '1', '0', '0', '1'), - ('1', '1', '1', '1', '1')); - begin - -- Check each pattern. - for i in patterns'range loop - -- Set the inputs. - i0 <= patterns(i).i0; - i1 <= patterns(i).i1; - ci <= patterns(i).ci; - -- Wait for the results. - wait for 1 ns; - -- Check the outputs. - assert s = patterns(i).s - report "bad sum value" severity error; - assert co = patterns(i).co - report "bad carry out value" severity error; - end loop; - assert false report "end of test" severity note; - -- Wait forever; this will finish the simulation. - wait; - end process; - end behav; + -- A testbench has no ports. + entity adder_tb is + end adder_tb; + + architecture behav of adder_tb is + -- Declaration of the component that will be instantiated. + component adder + port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); + end component; + + -- Specifies which entity is bound with the component. + for adder_0: adder use entity work.adder; + signal i0, i1, ci, s, co : bit; + begin + -- Component instantiation. + adder_0: adder port map (i0 => i0, i1 => i1, ci => ci, + s => s, co => co); + + -- This process does the real job. + process + type pattern_type is record + -- The inputs of the adder. + i0, i1, ci : bit; + -- The expected outputs of the adder. + s, co : bit; + end record; + -- The patterns to apply. + type pattern_array is array (natural range <>) of pattern_type; + constant patterns : pattern_array := + (('0', '0', '0', '0', '0'), + ('0', '0', '1', '1', '0'), + ('0', '1', '0', '1', '0'), + ('0', '1', '1', '0', '1'), + ('1', '0', '0', '1', '0'), + ('1', '0', '1', '0', '1'), + ('1', '1', '0', '0', '1'), + ('1', '1', '1', '1', '1')); + begin + -- Check each pattern. + for i in patterns'range loop + -- Set the inputs. + i0 <= patterns(i).i0; + i1 <= patterns(i).i1; + ci <= patterns(i).ci; + -- Wait for the results. + wait for 1 ns; + -- Check the outputs. + assert s = patterns(i).s + report "bad sum value" severity error; + assert co = patterns(i).co + report "bad carry out value" severity error; + end loop; + assert false report "end of test" severity note; + -- Wait forever; this will finish the simulation. + wait; + end process; + end behav; As usual, you should analyze the design, ``ghdl -a adder_tb.vhdl``. @@ -168,11 +168,11 @@ Now, it is time to run the testbench, ``ghdl -r adder_tb``, and check the result adder_tb.vhdl:52:7:(assertion note): end of test -If your design is rather complex, you'd like to inspect signals. Signal values can be dumped using multiple formats (see section ':ref:`export_waves`' for more information). The resulting file can be read with a wave viewer such as `GtkWave <http://gtkwave.sourceforge.net/>`_. +If your design is rather complex, you'd like to inspect signals. Signal values can be dumped using multiple formats (see section :ref:`export_waves` for more information). The resulting file can be read with a wave viewer such as `GtkWave <http://gtkwave.sourceforge.net/>`_. As explained in the `manual <http://gtkwave.sourceforge.net/gtkwave.pdf>`_, GtkWave *'relies on a post-mortem approach through the use of dumpfiles'*. Therefore, you should first simulate your design and dump a waveform file, say VCD: ``ghdl -r adder_tb --vcd=adder.vcd``. Then, you can view the dump: ``gtkwave adder.vcd``. -See section ':ref:`simulation_options`', for more details on other runtime options. +See section :ref:`simulation_options`, for more details on other runtime options. Starting with a design ====================== @@ -181,16 +181,16 @@ Unless you are only studying VHDL, you will work with larger designs than the on - First, untar the sources: ``tar zxvf dlx.tar.gz``. -.. HINT:: In order not to pollute the sources with the library, it is a good idea to create a :file:`work/` subdirectory for the `WORK` library. To any GHDL commands, we will add the :option:`--workdir=work` option, so that all files generated by the compiler (except the executable) will be placed in this directory. +.. HINT:: In order not to pollute the sources with the library, it is a good idea to create a :file:`work/` subdirectory for the `WORK` library. To any GHDL commands, we will add the :option:`--workdir=work` option, so that all files generated by the compiler (except the executable) will be placed in this directory. .. code-block:: shell $ cd dlx $ mkdir work -* Then, we will run the ``dlx_test_behaviour`` design. We need to analyze all the design units for the design hierarchy, in the correct order. GHDL provides an easy way to do this, by importing the sources, ``ghdl -i --workdir=work *.vhdl``. +* Then, we will run the ``dlx_test_behaviour`` design. We need to analyze all the design units for the design hierarchy, in the correct order. GHDL provides an easy way to do this, by importing the sources, ``ghdl -i --workdir=work *.vhdl``. -* GHDL knows all the design units of the DLX, but no one have been analyzed. Run the make option, ``ghdl -m --workdir=work dlx_test_behaviour``, which analyzes and elaborates a design. This creates many files in the :file:`work/` directory, and (GCC/LLVM only) the :file:`dlx_test_behaviour` executable in the current directory. +* GHDL knows all the design units of the DLX, but none of them has been analyzed. Run the make option, ``ghdl -m --workdir=work dlx_test_behaviour``, which analyzes and elaborates a design. This creates many files in the :file:`work/` directory, and (GCC/LLVM only) the :file:`dlx_test_behaviour` executable in the current directory. .. HINT:: The simulation needs to have a DLX program contained in the file :file:`dlx.out`. This memory image will be loaded in the DLX memory. Just take one sample: ``cp test_loop.out dlx.out``. @@ -201,7 +201,7 @@ Unless you are only studying VHDL, you will work with larger designs than the on dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction encountered, execution halted -* Last, since the clock is still running, you have to manually stop the program with the :kbd:`C-c` key sequence. This behavior prevents you from running the test bench in batch mode. However, you may force the simulator to stop when an assertion above or equal a certain severity level occurs. To do so, call run with this option instead: ``ghdl -r --workdir=work dlx_test_behaviour --assert-level=note```. With this option, the program stops just after the previous message: +* Lastly, since the clock is still running, you have to manually stop the program with the :kbd:`C-c` key sequence. This behavior prevents you from running the test bench in batch mode. However, you may force the simulator to stop when an assertion above or equal a certain severity level occurs. To do so, call run with this option instead: ``ghdl -r --workdir=work dlx_test_behaviour --assert-level=note```. With this option, the program stops just after the previous message: .. code-block:: shell @@ -212,7 +212,7 @@ Unless you are only studying VHDL, you will work with larger designs than the on .. TIP:: If you want to make room on your hard drive, you can either: * Clean the design library with the GHDL command ``ghdl --clean --workdir=work``. This removes the executable and all the object files. If you want to rebuild the design at this point, just do the make command as shown above. - * Remove the design library with the GHDL command ``ghdl --remove --workdir=work``. This removes the executable, all the object files and the library file. If you want to rebuild the design, you have to import the sources again, and to make the design. + * Remove the design library with the GHDL command ``ghdl --remove --workdir=work``. This removes the executable, all the object files and the library file. If you want to rebuild the design, you have to import the sources again and make the design. * Remove the :file:`work/` directory: ``rm -rf work``. Only the executable is kept. If you want to rebuild the design, create the :file:`work/` directory, import the sources, and make the design. -.. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it uses the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section ':ref:`IEEE_library_pitfalls`', for more details. +.. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it might use the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section :ref:`IEEE_library_pitfalls`, for more details. diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst index 6200d82a7..8bb43b941 100644 --- a/doc/using/Simulation.rst +++ b/doc/using/Simulation.rst @@ -10,12 +10,12 @@ Simulation options ================== In most system environments, it is possible to pass options while -invoking a program. Contrary to most programming languages, there is no +invoking a program. Contrary to most programming languages, there is no standard method in VHDL to obtain the arguments or to set the exit status. -In GHDL, it is impossible to pass parameters to your design. A later version -could do it through the generics interfaces of the top entity. +In GHDL, it is impossible to pass parameters to your design. A later version +could do it through the generic interfaces of the top entity. However, the GHDL runtime behaviour can be modified with some options; for example, it is possible to stop simulation after a certain time. @@ -24,14 +24,14 @@ The exit status of the simulation is ``EXIT_SUCCESS`` (0) if the simulation completes, or ``EXIT_FAILURE`` (1) in case of error (assertion failure, overflow or any constraint error). -Here is the list of the most useful options. Some debugging options are -also available, but not described here. The :option:`--help` options lists +Here is the list of the most useful options. Some debugging options are +also available, but not described here. The :option:`--help` option lists all options available, including the debugging one. .. option:: --assert-level<=LEVEL> Select the assertion level at which an assertion violation stops the - simulation. `LEVEL` is the name from the `severity_level` + simulation. `LEVEL` is the name from the `severity_level` enumerated type defined in the `standard` package or the ``none`` name. @@ -43,23 +43,23 @@ all options available, including the debugging one. stop simulation, but the assertion violation at the ``note`` severity level would only display a message. - Option :option:`--assert-level=none` prevents any assertion violation to stop + Option :option:`--assert-level=none` prevents any assertion violation from stopping simulation. .. option:: --ieee-asserts<=POLICY> Select how the assertions from ``ieee`` units are handled. `POLICY` can be ``enable`` (the default), - ``disable`` which disables all assertion from ``ieee`` packages - and ``disable-at-0`` which disables only at start of simulation. + ``disable`` which disables all assertions from ``ieee`` packages + and ``disable-at-0`` which disables only at the start of simulation. - This option can be useful to avoid assertion message from + This option can be useful to avoid assertion messages from ``ieee.numeric_std`` (and other ``ieee`` packages). .. option:: --stop-time<=TIME> - Stop the simulation after ``TIME``. ``TIME`` is expressed as a time - value, *without* any space. The time is the simulation time, not + Stop the simulation after ``TIME``. ``TIME`` is expressed as a time + value, *without* any space. The time is the simulation time, not the real clock time. For example:: @@ -86,8 +86,8 @@ all options available, including the debugging one. Do VITAL annotation on `PATH` with SDF file :file:`FILENAME`. `PATH` is a path of instances, separated with ``.`` or ``/``. - Any separator can be used. Instances are component instantiation labels, - generate labels or block labels. Currently, you cannot use an indexed name. + Any separator can be used. Instances are component instantiation labels, + generate labels or block labels. Currently, you cannot use an indexed name. Specifying a delay:: @@ -97,18 +97,18 @@ all options available, including the debugging one. If the option contains a type of delay, that is ``min=``, ``typ=`` or ``max=``, the annotator use respectively minimum, - typical or maximum values. If the option does not contain a type of delay, - the annotator use the typical delay. + typical or maximum values. If the option does not contain a type of delay, + the annotator uses the typical delay. - See section ':ref:`Backannotation`', for more details. + See section :ref:`Backannotation`, for more details. .. option:: --vpi<=FILENAME> -Load VPI module. + Load VPI module. .. option:: --vpi-trace<=FILE> -Trace vpi calls to FILE. + Trace vpi calls to FILE. .. option:: --help @@ -134,21 +134,21 @@ Export waveforms # Path format for signals in entities : /top/sub/clk - # Dumps every signals named reset in first level sub entities of top + # Dump every signal named reset in first level sub entities of top /top/*/reset - # Dumps every signals named reset in recursive sub entities of top + # Dump every signal named reset in recursive sub entities of top /top/**/reset - # Dump every signals of sub2 which could be anywhere in design except on - # top level + # Dump every signal of sub2 which could be anywhere in the design except + # on the top level /**/sub2/* - # Dump every signals of sub3 which must be a first level sub entity of the + # Dump every signal of sub3 which must be a first level sub entity of the # top level /*/sub3/* - # Dump every signals of the first level sub entities of sub3 (but not + # Dump every signal of the first level sub entities of sub3 (but not # those of sub3) /**/sub3/*/* @@ -169,19 +169,19 @@ Export waveforms .. index:: dump of signals Option :option:`--vcd` dumps into the VCD file `FILENAME` the signal - values before each non-delta cycle. If `FILENAME` is ``-``, + values before each non-delta cycle. If `FILENAME` is ``-``, then the standard output is used, otherwise a file is created or overwritten. The :option:`--vcdgz` option is the same as the *--vcd* option, but the output is compressed using the `zlib` (`gzip` - compression). However, you can't use the ``-`` filename. + compression). However, you can't use the ``-`` filename. Furthermore, only one VCD file can be written. :dfn:`VCD` (value change dump) is a file format defined by the `verilog` standard and used by virtually any wave viewer. - Since it comes from `verilog`, only a few VHDL types can be dumped. GHDL + Since it comes from `verilog`, only a few VHDL types can be dumped. GHDL dumps only signals whose base type is of the following: * types defined in the ``std.standard`` package: @@ -204,27 +204,27 @@ Export waveforms dumped, which can generate big files. It is very unfortunate there is no standard or well-known wave file - format supporting VHDL types. If you are aware of such a free format, + format supporting VHDL types. If you are aware of such a free format, please mail me (:ref:`Reporting_bugs`). .. option:: --vcd-nodate - Do not write date in VCD file + Do not write date in the VCD file. .. option:: --fst<=FILENAME> - Write the waveforms into a `fst`, that can be displayed by + Write the waveforms into an `fst` file that can be displayed by `gtkwave`. The `fst` files are much smaller than VCD or `GHW` files, but it handles only the same signals as the VCD format. .. option:: --wave<=FILENAME> - Write the waveforms into a `ghw` (GHdl Waveform) file. Currently, all + Write the waveforms into a `ghw` (GHdl Waveform) file. Currently, all the signals are dumped into the waveform file, you cannot select a hierarchy of signals to be dumped. The format of this file was defined by myself and is not yet completely fixed. - It may change slightly. The ``gtkwave`` tool can read the GHW files. + It may change slightly. The ``gtkwave`` tool can read the GHW files. Contrary to VCD files, any VHDL type can be dumped into a GHW file. @@ -239,17 +239,13 @@ Export hierarchy and references This may be useful to understand the structure of a complex design. `KIND` is optional, but if set must be one of: - * none - Do not display hierarchy. Same as if the option was not present. + * ``none`` Do not display hierarchy. Same as if the option was not present. - * inst - Display entities, architectures, instances, blocks and generates statements. + * ``inst`` Display entities, architectures, instances, blocks and generates statements. - * proc - Like ``inst`` but also display processes. + * ``proc`` Like ``inst`` but also display processes. - * port - Like ``proc`` but display ports and signals too. + * ``port`` Like ``proc`` but display ports and signals too. If `KIND` is not specified, the hierarchy is displayed with the ``port`` mode. @@ -259,21 +255,21 @@ Export hierarchy and references .. option:: --xref-html <[options] file...> -To easily navigate through your sources, you may generate cross-references. This command generates an html file for each ``file`` given in the command line, with syntax highlighting and full cross-reference: every identifier is a link to its declaration. Besides, an index of the files is created too. + To easily navigate through your sources, you may generate cross-references. This command generates an html file for each ``file`` given in the command line, with syntax highlighting and full cross-reference: every identifier is a link to its declaration. An index of the files is created too. -The set of ``file`` are analyzed, and then, if the analysis is successful, html files are generated in the directory specified by the :option:`-o <dir>` option, or :file:`html/` directory by default. + The set of ``file`` are analyzed, and then, if the analysis is successful, html files are generated in the directory specified by the :option:`-o <dir>` option, or :file:`html/` directory by default. -* If the option :option:`--format=html2` is specified, then the generated html files follow the HTML 2.0 standard, and colours are specified with `<FONT>` tags. However, colours are hard-coded. + * If the option :option:`--format=html2` is specified, then the generated html files follow the HTML 2.0 standard, and colours are specified with `<FONT>` tags. However, colours are hard-coded. -* If the option :option:`--format=css` is specified, then the generated html files follow the HTML 4.0 standard, and use the CSS-1 file :file:`ghdl.css` to specify colours. This file is generated only if it does not already exist (it is never overwritten) and can be customized by the user to change colours or appearance. Refer to a generated file and its comments for more information. + * If the option :option:`--format=css` is specified, then the generated html files follow the HTML 4.0 standard, and use the CSS-1 file :file:`ghdl.css` to specify colours. This file is generated only if it does not already exist (it is never overwritten) and can be customized by the user to change colours or appearance. Refer to a generated file and its comments for more information. .. option:: --psl-report<=FILENAME> -Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but still being human readable. + Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but is still human readable. .. option:: --file-to-xml -Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation... + Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation, etc. .. WARNING:: * The AST slightly changes from time to time (particularly when new nodes are added for new language features), so be liberal in what is allowed by your tool. Also, the XML can be quite large so consider it only during prototyping. @@ -287,51 +283,51 @@ Debugging .. option:: --trace-signals -Display signals after each cycle. + Display signals after each cycle. .. option:: --trace-processes -Display process name before each cycle. + Display process name before each cycle. .. option:: --stats -Display run-time statistics. + Display run-time statistics. .. option:: --disp-order -Display signals order. + Display signals order. .. option:: --disp-sources -Display sources while displaying signals. + Display sources while displaying signals. .. option:: --disp-sig-types -Display signal types. + Display signal types. .. option:: --disp-signals-map -Display map bw declared signals and internal signals. + Display map bw declared signals and internal signals. .. option:: --disp-signals-table -Display internal signals. + Display internal signals. .. option:: --checks -Do internal checks after each process run. + Do internal checks after each process run. .. option:: --activity<=LEVEL> -Watch activity of LEVEL signals: LEVEL is all, min (default) or none (unsafe). + Watch activity of LEVEL signals: LEVEL is ``all``, ``min`` (default) or ``none`` (unsafe). .. option:: --dump-rti -Dump Run Time Information (RTI). + Dump Run Time Information (RTI). .. option:: --bootstrap -Allow ``--work=std`` + Allow ``--work=std`` GNU Debugger (GDB) ------------------ @@ -342,7 +338,7 @@ GNU Debugger (GDB) GDB is a general purpose debugger for programs compiled by GCC. Currently, there is no VHDL support for GDB. It may be difficult to inspect variables or signals in GDB. However, it is still able to display the stack frame in case of error or to set a breakpoint at a specified line. -GDB can be useful to precisely catch a runtime error, such as indexing an array beyond its bounds. All error check subprograms call the ``__ghdl_fatal`` procedure. Therefore, to catch runtime error, set a breakpoint like this:: +GDB can be useful to catch a runtime error, such as indexing an array beyond its bounds. All error check subprograms call the ``__ghdl_fatal`` procedure. Therefore, to a catch runtime error, set a breakpoint like this:: (gdb) break __ghdl_fatal |